参数资料
| 型号： | NCP5331FTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 34/36页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM 2PH W/DRVRS 32-LQFP |
| 产品变化通告： | Product Obsolescence 05/Oct/2010 |
| 标准包装： | 1 |
| 应用： | 控制器，AMD Athlon? |
| 输入电压： | 9 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 5V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5331FTR2GOSCT |
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NCP5331
Equation 28 is used to calculate the heat sink thermal
impedances necessary to maintain less than the specified
maximum junction temperatures at 55 ° C ambient.
7. Current Sensing
Choose the current sense network (R Sx , C Sx , x = 1 or 2) to
satisfy
q CNTRLSA t (120 * 55 ° C) 1.48 W * 1.65 ° C W
RSx @ CSx + Lo (RL ) RPCB)
(32)
+ 42.3 ° C W
q SYNCHSA t (120 * 55 ° C) 0.85 W * 1.65 ° C W
+ 74.8 ° C W per MOSFET
or 37.4 ° C W per phase for two MOSFETs phase
If board area permits, a cost effective heatsink could be
formed by using a TO?263 mounting pad of at least 2.0 in 2
(1282 mm 2 ) for the upper and lower MOSFETs on a
single?sided, 1 oz copper PCB. The total required pad area
would be slightly less if the area were divided evenly
between top and bottom layers with multiple thermal vias
joining the two areas. To conserve board space, AAVID
offers clip?on heatsinks for TO?220 thru?hole packages.
Examples of these heatsinks include #577002 (1 ″ × 0.75 ″ ×
0.25 ″ , 33 ° C/W at 2 W) and #591302 (0.75 ″ × 0.5 ″ × 0.5 ″ ,
29 ° C/W at 2 W).
6. Adaptive Voltage Positioning
First, to achieve the 200 kHz switching frequency, use
Figure 5 to determine that a 51 k W resistor is needed for
R OSC . Then, use Figure 6 to find the V FB bias current at the
corresponding value of R OSC . In this example, the 51 k W
R OSC resistor results in a V FB bias current of approximately
7.0 m A. Knowing the V FB bias current, one can calculate the
required values for R F1 and R DRP using Equation 29 through
Equation 31.
The no?load position is easily set using Equation 29.
Equation 32 will be most accurate for better iron powder
core material (such as the ?8 from Micrometals). This
material is very consistent with dc current and frequency.
Less expensive core materials (such as the ?52 from
Micrometals) change their characteristics with dc current,
ac flux density, and frequency. This material will yield
acceptable converter performance if the current sense time
constant is set lower (longer) than anticipated. As a rule of
thumb, start with approximately twice the resistance (R Sx )
or twice the capacitance (C Sx ) when using the less expensive
core material.
The component values determined thus far are L o = 828 nH,
R L = 0.965 m W , and R PCB = 0.2 m W . We choose a convenient
value for C S1 (0.1 m F) and solve for R Sx .
RSn + 828 nH (0.965 m W ) 0.2 m W ) @ 0.1 m F
+ 7.10 k W
After the circuit is constructed, the values of R Sx and/or
C Sx should be tuned to provide a “square?wave” at the V DRP
pin with minimal overshoot and fast rise time due to a step
change in load current as shown in Figure 35, Figure 36 and
Figure 37. This testing has shown that for a 3 to 25 A
transient, a value of 10.0 k W will produce the desired square
wave at V DRP.
8. Error Amplifier Tuning
The error amplifier is tuned by adjusting C A1 to provide
an acceptable full?load transient response as shown in
RVFBK + D VNO?LOAD IBIASVFB
(29)
Figure 38, Figure 39 and Figure 40. After a value for C A1 is
+ +25 mV 7.0 m A
+ 3.6 k W
For inductive current sensing, the designer must calculate
the inductor ’s resistance (R L ) and approximate any
resistance added by the circuit board (R PCB ). We found the
inductor ’s nominal resistance in Section 2 (0.965 m W ). In
this example, we assume 0.2 m W for the circuit board
resistance (R PCB ). With this information, Equation 30 can
be used to calculate the increase at the V DRP pin at full load.
chosen, the peak?to?peak voltage ripple on the COMP pin
is examined under full?load to insure less than 20 mVpp as
shown in Figure 41.
9. Current Limit Setting
The maximum inductor resistance, the maximum PCB
resistance, and the maximum current?sense gain determine
the current limit as shown in Equation 34. The maximum
current, I OUT,LIMIT , was specified in the design
requirements. The maximum inductor resistance occurs at
full load and the highest ambient temperature. This value
D VDRP
(IBIASVFB ) D VCORE,FULL?LOAD RF1)
D VDRP + IO,MAX @ (RL ) RPCB) @ GVDRP
+ 52 A @ (0.965 m W ) 0.2 m W ) @ 4.2 V V
+ 0.254 mV
R DRP can then be calculated from Equation 31.
RDRP +
+ 254 mV (7.0 m A ) 37 mV 3.6 k W )
+ 14.7 k W
(30)
(31)
was found in the “Output Inductor Section” (1.28 m W ). This
analysis assumes the PCB resistance only increases due to
the change in ambient temperature. Component heating will
also increase the PCB temperature but quantifying this
effect is difficult. Lab testing should be used to “fine tune”
the overcurrent threshold.
RPCB,MAX + 0.2 m W @ {1 ) 0.39% ° C
@ (100 ° C * 25 ° C)}
+ 0.26 m W
http://onsemi.com
34
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