参数资料
型号: NCP5331FTR2G
厂商: ON Semiconductor
文件页数: 32/36页
文件大小: 0K
描述: IC CTLR PWM 2PH W/DRVRS 32-LQFP
产品变化通告: Product Obsolescence 05/Oct/2010
标准包装: 1
应用: 控制器,AMD Athlon?
输入电压: 9 V ~ 14 V
输出数: 2
输出电压: 5V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-LQFP(7x7)
包装: 剪切带 (CT)
其它名称: NCP5331FTR2GOSCT
NCP5331
2. Output Inductor Selection
Next, use Equation 6 to Equation 10 with the full?load
(VIN * VOUT) @ VOUT
( a @ IO,MAX @ VIN @ fSW)
+
+ (12 V * 1.163 V) @
Calculate the minimum output inductance at I O,MAX
according to Equation 3 with ± 20% inductor ripple current
( α = 0.15).
(3)
LoMIN +
(12 V * 1.163 V) @ 1.163 V
(0.15 @ 52 A @ 12 V @ 200 kHz)
+ 673 nH
To minimize core losses, we choose the T50 ? 8B/90 core
from Micrometals: 23.0 nH/N 2 , 2.50 cm/turn. According to
the Micrometals catalog, at 26 A (per phase) the
permeability of this core will be approximately 88% of the
permeability at 0 A. Therefore, at 0 A we must achieve at
least 673 nH/0.88 or 765 nH. Using 6 turns of #16 AWG
bifilar (2 m W /ft) will produce 828 nH .
We will need the nominal and worst case inductor
resistances for subsequent calculations.
RL + 6 turns @ 2.5 cm turn @ 0.03218 ft cm @ 2 m W ft
+ 0.965 m W
inductance value of 729 nH.
D ILo + (VIN * VOUT) @ D (Lo @ fSW)
(1.163 V 12 V)
(729 nH @ 200 kHz)
+ 7.20 App
ILo,MAX + IO,MAX 2 ) D ILo 2
+ 52 A 2 ) 7.20 App 2 + 29.6 A
ILo,MIN + IO,MAX 2 * D ILo 2
+ 52 A 2 * 7.20 App 2 + 22.4 A
IC,MAX + ILo,MAX h * IIN,AVG
+ 29.6 A 0.80 * 6.30 A + 30.7 A
IC,MIN + ILo,MIN h * IIN,AVG
+ 22.4 A 0.80 * 6.30 A + 21.7 A
(10)
(8)
(9)
(6)
(7)
ICIN,RMS + [2D @ (IC,MIN2 ) IC,MIN @ D IC,IN
The inductor resistance will be maximized when the
inductor is “hot” due to the load current and the ambient
temperature is high. Assuming a 50 ° C temperature rise of
the inductor at full?load and a 35 ° C ambient temperature
rise we can calculate
RL,MAX + 0.965 m W @ [1 ) 0.39% ° C @ (50 ° C ) 35 ° C)]
+ 1.28 m W
The output inductance at full?load will be reduced due to
the saturation characteristic of the core material.
Lo52 A + 0.88 828 nH + 729 nH at full load
Next, use Equation 4 to insure the output voltage ripple
will satisfy the design goal with the minimum number of
output capacitors and the full load output inductance.
VOUT,P?P + (ESR per cap NOUT,MIN) (4)
@ {(VIN * #Phases @ VCORE) @ D (Lo52 A @ fSW)}
+ (19 m W 6) @ {(12 V * 2 @ 1.163 V)
@ (1.163 V 12 V) (729 nH @ 200 kHz)}
+ 20 mV
So, the ripple requirement will be satisfied if the minimum
number of output capacitors is used. More output capacitors
will probably be required to satisfy the transient
requirement, which will result in a lower ripple voltage.
3. Input Capacitor Selection
Use Equation 5 to determine the average input current to
the converter at full?load.
For the two?phase converter, the input capacitor(s) rms
current at full?load is as follows. (Note: D = 1.163 V/12 V
= 0.097.)
(11)
) D IC,IN2 3) ) IIN,AVG2 @ (1 * 2D)]1 2
+ [0.19 @ (21.72 ) 21.7 @ 9.0 ) 9.02 3)
) 6.302 @ (1 * 0.19)]1 2
+ 12.9 ARMS
At this point, the designer must decide between saving
board space by using higher?rated/more costly capacitors
or saving cost by using more lower?rated/less costly
capacitors. To save cost, we choose the MBZ series
capacitors by Rubycon. Part number 16MBZ1500M10X20:
1500 m F, 16 V, 2.55 A RMS , 13 m W , 10 × 20 mm. This design
will require N IN = 12.8 A/2.55 A = 5 capacitors on the input
for a cost sensitive design or 6 capacitors for a conservative
design.
4. Input Inductor Selection
For the Claw Hammper CPU, the input inductor must
limit the input current slew rate to less than 0.5 A/ m s during
a load transient from 0 to 52 A. A conservative value will be
calculated assuming the minimum number of output
capacitors (N OUT = 6), five input capacitors (N IN = 5), worst
case ESR values for both the input and output capacitors,
and a maximum duty cycle at the maximum DAC setting
with 25 mV of no?load AVP.
DMAX + (1.550 V ) 25 mVAVP) 10.8 VIN + 0.146
IIN,AVG + IO,MAX @ D h
(5)
+ 52 A @ (1.163 V 12 V) 0.80 + 6.30 A
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