参数资料
| 型号： | NCP5332ADWR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/30页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK 2PH STEPDWN 28SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 1 |
| 应用： | 控制器，高性能处理器 |
| 输入电压： | 4.5 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5332ADWR2OSCT |
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NCP5332A
Enhanced V 2 responds to disturbances in V CORE by
employing both “slow” and “fast” voltage regulation. The
internal error amplifier performs the slow regulation.
Depending on the gain and frequency compensation set by
the amplifier ’s external components, the error amplifier will
typically begin to ramp its output to react to changes in the
output voltage in 1?2 PWM cycles. Fast voltage feedback is
implemented by a direct connection from V CORE to the
non?inverting pin of the PWM comparator via the
summation with the inductor current, internal ramp, and
Offset. A rapid increase in load current will produce a
negative offset at V CORE and at the output of the summer.
This will cause the PWM duty cycle to increase almost
instantly. Fast feedback will typically adjust the PWM duty
cycle in 1 PWM cycle.
As shown in Figure 10, an internal ramp (nominally 125 mV
at a 50% duty cycle) is added to the inductor current ramp
at the positive terminal of the PWM comparator. This
additional ramp compensates for propagation time delays
from the current sense amplifier (CSA), the PWM
comparator, and the MOSFET gate drivers. As a result, the
minimum ON time of the controller is reduced and lower
duty cycles may be achieved at higher frequencies. Also, the
additional ramp reduces the reliance on the inductor current
ramp and allows greater flexibility when choosing the output
inductor and the R CSn C CSn (n = 1 or 2) time constant of the
feedback components from V CORE to the CSn pin.
Including both current and voltage information in the
feedback signal allows the open loop output impedance of
the power stage to be controlled. When the average output
current is zero, the COMP pin will be:
VCOMP + VOUT @ 0 A ) Channel_Startup_Offset
) Int_Ramp ) GCSA @ Ext_Ramp 2
Int_Ramp is the “partial” internal ramp value at the
corresponding duty cycle, Ext_Ramp is the peak?to?peak
external steady?state ramp at 0 A, G CSA is the Current Sense
Amplifier Gain (nominally 3.5 V/V), and the Channel
Startup Offset is typically 0.40 V. The magnitude of the
Ext_Ramp can be calculated from:
Ext_Ramp + D @ (VIN * VOUT) (RCSn @ CCSn @ fSW)
For example, if V OUT at 0 A is set to 1.630 V with AVP
and the input voltage is 12.0 V, the duty cycle (D) will be
1.630/12.0 or 13.6%. Int_Ramp will be 125 mV ? 13.6/50 =
34 mV. Realistic values for R CSn , C CSn and f SW are 60 k ? ,
0.01 μ F, and 220 kHz ? using these and the previously
mentioned formula, Ext_Ramp will be 10.6 mV.
VCOMP + 1.630 V ) 0.40 V ) 34 mV
Or, in a closed loop configuration when the output current
changes, the COMP pin must move to keep the same output
voltage. The required change in the output voltage or COMP
pin depends on the scaling of the current feedback signal and
is calculated as:
D V + RS @ GCSA @ D IOUT.
The single?phase power stage output impedance is:
Single Stage Impedance + D VOUT D IOUT + RS @ GCSA
The multi?phase power stage output impedance is the
single?phase output impedance divided by the number of
phases. The output impedance of the power stage determines
how the converter will respond during the first few
microseconds of a transient before the feedback loop has
repositioned the COMP pin.
The peak output current can be calculated from:
IOUT,PEAK + (VCOMP * VOUT * Offset) (RS @ GCSA)
Figure 11 shows the step response of the COMP pin at a
fixed level. Before T1 the converter is in normal steady state
operation. The inductor current provides a portion of the
PWM ramp through the Current Sense Amplifier. The PWM
cycle ends when the sum of the current ramp, the “partial”
internal ramp voltage signal and Offset exceed the level of
the COMP pin. At T1 the output current increases and the
output voltage sags. The next PWM cycle begins and the
cycle continues longer than previously while the current
signal increases enough to make up for the lower voltage at
the V FB pin and the cycle ends at T2. After T2 the output
voltage remains lower than at light load and the average
current signal level (CSn output) is raised so that the sum of
the current and voltage signal is the same as with the original
load. In a closed loop system the COMP pin would move
higher to restore the output voltage to the original level.
SWNODE
V FB (V OUT )
Internal Ramp
CSA Out w/
Exaggerated
Delays
COMP?Offset
) 3.5 V V @ 10.6 mV 2
+ 2.083 Vdc.
CSA Out + Ramp + CS REF
T1
T2
If the COMP pin is held steady and the inductor current
changes, there must also be a change in the output voltage.
http://onsemi.com
13
Figure 11. Open Loop Operation
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