参数资料
| 型号： | NCP5332ADWR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 19/30页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK 2PH STEPDWN 28SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 1 |
| 应用： | 控制器，高性能处理器 |
| 输入电压： | 4.5 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5332ADWR2OSCT |
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NCP5332A
IC,MAX + ILo,MAX h * IIN,AVG
IC,MIN + ILo,MIN h * IIN,AVG
I Lo,MAX is the maximum output inductor current:
ILo,MAX + IO,MAX 2 ) D ILo 2
I Lo,MIN is the minimum output inductor current:
ILo,MIN + IO,MAX 2 * D ILo 2
(6)
(7)
(8)
(9)
derating. The designer should be cognizant of the ESR of the
input capacitors. The input capacitor power loss can be
calculated from:
PCIN + ICIN,RMS2 @ ESR_per_capacitor NIN (13)
Low ESR capacitors are recommended to minimize losses
and reduce capacitor heating. The life of an electrolytic
capacitor is reduced 50% for every 10 ° C rise in the
capacitor ’s temperature.
? I Lo is the peak?to?peak ripple current in the output
inductor of value Lo:
4. Input Inductor Selection
The use of an inductor between the input capacitors and
D ILo + (VIN * VOUT) @ D (Lo @ fSW)
(10)
the power source will accomplish two objectives. First, it
will isolate the voltage source and the system from the noise
For the two?phase converter, the input capacitor(s) RMS
current is then:
generated in the switching supply. Second, it will limit the
inrush current into the input capacitors at power up. Large
ICIN,RMS + [2D @ (IC,MIN2 ) IC,MIN @ D IC,IN
(11)
inrush currents will reduce the expected life of the input
capacitors. The inductor ’s limiting effect on the input
) D IC,IN2 3) ) IIN,AVG2 @ (1 * 2D)]1 2
Select the number of input capacitors (N IN ) to provide the
RMS input current (I CIN,RMS ) based on the RMS ripple
current rating per capacitor (I RMS,RATED ):
current slew rate becomes increasingly beneficial during
load transients.
The worst case input current slew rate will occur during
the first few PWM cycles immediately after a step?load
change is applied as shown in Figure 16. When the load is
NIN + ICIN,RMS IRMS,RATED
(12)
applied, the output voltage is pulled down very quickly.
Current through the output inductors will not change
VOUT,FULL?LOAD +
For a two?phase converter with perfect efficiency ( η = 1),
the worst case input ripple?current will occur when the
converter is operating at a 25% duty cycle. At this operating
point, the parallel combination of input capacitors must
support an RMS ripple current equal to 25% of the
converter ’s DC output current. At other duty cycles, the
ripple?current will be less. For example, at a duty cycle of
either 10% or 40%, the two?phase input ripple?current will
be approximately 20% of the converter’s DC output current.
In general, capacitor manufacturers require derating to the
specified ripple?current based on the ambient temperature.
More capacitors will be required because of the current
MAX dI/dt occurs in
first few PWM cycles.
instantaneously so the initial transient load current must be
conducted by the output capacitors. The output voltage will
step downward depending on the magnitude of the output
current (I O,MAX ), the per capacitor ESR of the output
capacitors (ESR OUT ), and the number of the output
capacitors (N OUT ) as shown in Figure 16. Assuming the load
current is shared equally between the two phases, the output
voltage at full, transient load will be:
(14)
VOUT,NO?LOAD * (IO,MAX 2) @ ESROUT NOUT
V OUT
I Li
Vi(t = 0) = 12 V
Q1
SWNODE
I Lo
Vo(t = 0) = 1.630 V
Li
TBD
Lo
700 nH
+ Vi
? 12 V
Ci
3 × 16SP270
ESR Ci
18 m/3 = 6.0 m
+ V Ci
Q2
+ Co
7 × 16MBZ1500M10X20
22.5 u(t)
ESR Co
13 m/7 = 1.9 m
Figure 16. Calculating the Input Inductance
http://onsemi.com
19
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