参数资料
| 型号： | NCP5332ADWR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 17/30页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK 2PH STEPDWN 28SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 1 |
| 应用： | 控制器，高性能处理器 |
| 输入电压： | 4.5 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5332ADWR2OSCT |
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NCP5332A
3. Place the components associated with the internal
error amplifier (R FBK1 , C FBK2 , C AMP , R CMP1 ,
C CMP1 , R DRP1 ) to minimize the trace lengths to
the pins V FB , V DRP and COMP.
4. Place the current sense components (R CS1 , R CS2 ,
C CS1 , C CS2 , R CSREF , C CSREF ) near the CS1, CS2,
and CS REF pins.
5. Place the frequency setting resistor (R OSC ) close to
the R OSC pin. The R OSC pin is very sensitive to
noise. Route noisy traces, such as the SWNODEs
and GATE traces, away from the R OSC pin and
resistor.
6. Place the Soft Start capacitor (C SS ) near the Soft
Start pin.
7. Place the MOSFETs and output inductors to
reduce the size of the noisy SWNODEs. There is a
trade?off between reducing the size of the
SWNODEs for noise reduction and providing
adequate heat?sinking for the synchronous
MOSFETs.
8. Place the input inductor and input capacitor(s) near
the Drain of the control (upper) MOSFETs. There
is a trade?off between reducing the size of this
node to save board area and providing adequate
heat?sinking for the control MOSFETs.
9. Place the output capacitors (electrolytic and ceramic)
close to the processor socket or output connector.
10. The trace from the SWNODEs to the current sense
components (R CS1 , R CS2 ) will be very noisy.
Route this away from more sensitive, low?level
traces. The Ground layer can be used to help
isolate this trace.
11. The Gate traces are very noisy. Route these away
from more sensitive, low?level traces. Keep each
Gate signal on one layer and insure that there is an
uninterrupted return path directly below the Gate
resistance added to the current sense paths. This
will insure acceptable current sharing. Also, route
the CS REF connection away from noisy traces such
as the SWNODEs and GATE traces. If noise from
the SWNODEs or GATE signals capacitively
couples to the CS REF trace the external ramps will
be very noisy and voltage jitter will result.
15. Ideally, the SWNODEs are exactly the same shape
and the current sense points (connections to R CS1
and R CS2 ) are made at identical locations to
equalize the PCB resistance added to the current
sense paths. This will help to insure acceptable
current sharing.
16. Place the 0.1 μ F ceramic capacitors, C Q1 and C Q2 ,
close to the drains of the MOSFETs Q1 and Q2,
respectively.
Design Procedure
1. Output Capacitor Selection
The output capacitors filter the current from the output
inductor and provide a low impedance for transient load
current changes. Typically, microprocessor applications
will require both bulk (electrolytic, tantalum) and low
impedance, high frequency (ceramic) types of capacitors.
The bulk capacitors provide “hold up” during transient
loading. The low impedance capacitors reduce steady?state
ripple and bypass the bulk capacitance when the output
current changes very quickly. The microprocessor
manufacturers usually specify a minimum number of
ceramic capacitors. The designer must determine the
number of bulk capacitors.
Choose the number of bulk output capacitors to meet the
peak transient requirements. The formula below can be used
to provide a starting point for the minimum number of bulk
capacitors (N OUT,MIN ):
trace. The Ground layer can be used to help isolate
these traces.
12. Don’t “daisy chain” connections to Ground from
NOUT,MIN + ESR per capacitor @
D IO,MAX
D VO,MAX
(1)
one via. Allow each connection to Ground to have
its own via as close to the component as possible.
13. Use a slot in the ground plane from the bulk output
capacitors back to the input power connector to
prevent high currents from flowing beneath the
control IC. This slot should extend length?wise
under the control IC and separate the connections
to “signal ground” and “power ground.” Examples
of signal ground include the capacitors at COMP,
CS REF , Soft?Start (SS) and REF, the resistors at
R OSC and I LIM , and the LGND pin to the controller.
Examples of power ground include the capacitors
to V CCH1 (and/or V CCH2 ) and V CCL1 (and/or
V CCL2 ), the Source of the synchronous MOSFET,
and the GND1 and GND2 pins of the controller.
14. The CS REF sense point should be equidistant
between the output inductors to equalize the PCB
In reality, both the ESR and ESL of the bulk capacitors
determine the voltage change during a load transient
according to:
D VO,MAX + ( D IO,MAX D t) @ ESL ) D IO,MAX @ ESR (2)
Unfortunately, capacitor manufacturers do not specify the
ESL of their components and the inductance added by the
PCB traces is highly dependent on the layout and routing.
Therefore, it is necessary to start a design with slightly more
than the minimum number of bulk capacitors and perform
transient testing or careful modeling/simulation to
determine the final number of bulk capacitors.
2. Output Inductor Selection
The output inductor may be the most critical component
in the converter because it will directly effect the choice of
other components and dictate both the steady?state and
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