参数资料
| 型号： | NCP5332ADWR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/30页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK 2PH STEPDWN 28SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 1 |
| 应用： | 控制器，高性能处理器 |
| 输入电压： | 4.5 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5332ADWR2OSCT |
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NCP5332A
ELECTRICAL CHARACTERISTICS (continued) (0 ° C < T A < 70 ° C; 0 ° C < T J < 125 ° C; 9.5 V < V CCH1 = V CCH2 < 20 V;
4.5 V < V CCL = V CCL1 = V CCL2 < 14 V; C GATE = 3.3 nF, R R(OSC) = 32.4 k ? , C COMP = 1.0 nF, C REF = 0.1 μ F, C SS = 0.1 μ F,
DAC Code 10000 (1.45 V), C VCC = 1.0 μ F; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
General Electrical Specifications
V CCH1 or V CCH2 Operating Current
V CCL Start Threshold
V CCL Stop Threshold
V CCL Hysteresis
V CCH1 Start Threshold
V CCH1 Stop Threshold
V CCH1 Hysteresis
V FB = COMP (no switching)
GATEs switching, Soft Start charging
GATEs stop switching, Soft Start discharging
GATEs not switching, Soft Start not charging
GATEs switching, Soft Start charging
GATEs stop switching, Soft Start discharging
GATEs not switching, Soft Start not charging
?
4.05
3.75
100
8.7
6.9
1.5
3.2
4.3
4.1
200
9.2
7.4
1.8
4.5
4.5
4.35
300
9.7
7.9
2.1
mA
V
V
mV
V
V
V
Reference Output
V REF Output Voltage
0 mA < I(V REF ) < 1.0 mA
3.2
3.3
3.4
V
Internal Ramp
Ramp Height @ 50% PWM
CS1 = CS2 = CS REF .
?
125
?
mV
Duty?Cycle
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
SO?28L
1
2
3
4?5
6
7
8?12
PIN SYMBOL
COMP
V FB
V DRP
CS1?CS2
CS REF
PWRGD
V ID4 ?V ID0
FUNCTION
Output of the error amplifier and input for the PWM
comparators.
Voltage Feedback Pin. To use Adaptive Voltage Positioning
(AVP) select an offset voltage at light load and connect a
resistor between V FB and V CORE . The output current of the
V FB pin and the resistor value determine output voltage off-
set for zero output current. Short V FB to V CORE for no AVP.
Current sense output for AVP. The offset of this pin above the
DAC voltage is proportional to the output current. Connect a
resistor from this pin to V FB to set amount AVP or leave this
pin open for no AVP. This pin’s maximum working voltage is
2.3 Vdc.
Current sense inputs. Connect current sense network for the
corresponding phase to each input. The input voltages to
these pins must be kept within 105 mV of CS REF or pulse?
by?pulse current limit will be tripped.
Reference for Current Sense Amplifiers, input to the Power
Good comparators, and fast feedback connection to the
PWM comparator. To balance input offset voltages between
the inverting and noninverting inputs of the Current Sense
Amplifiers, connect a resistor between CS REF and the output
voltage. The value should be 1/3 of the value of the resistors
connected to the CSx pins. The input voltage to this pin must
not exceed the maximum DAC (VID) setting by more than
100 mV or the internal PWM comparator may saturate.
Power Good Output. Open collector output goes low when
CS REF (V CORE ) is out of regulation.
Voltage ID DAC inputs. These pins are internally pulled up to
3.3 V if left open.
http://onsemi.com
8
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