参数资料
| 型号： | NCP5332ADWR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 20/30页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK 2PH STEPDWN 28SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 1 |
| 应用： | 控制器，高性能处理器 |
| 输入电压： | 4.5 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5332ADWR2OSCT |
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NCP5332A
When the control MOSFET (Q1 in Figure 16) turns ON,
the input voltage will be applied to the opposite terminal of
the output inductor (the SWNODE). At that instant, the
voltage across the output inductor can be calculated as:
Once the dissipation is known, the heat sink thermal
impedance can be calculated to prevent the specified
maximum case or junction temperatures from being exceeded
at the highest ambient temperature. Power dissipation has two
D VLo + VIN * VOUT,FULL?LOAD
+ VIN * VOUT,NO?LOAD
) (IO,MAX 2) @ ESROUT NOUT
(15)
primary contributors: conduction losses and switching losses.
The control or upper MOSFET will display both switching
and conduction losses. The synchronous or lower MOSFET
will exhibit only conduction losses because it switches into
nearly zero voltage. However, the body diode in the
The differential voltage across the output inductor will
cause its current to increase linearly with time. The slew rate
of this current can be calculated from:
synchronous MOSFET will suffer diode losses during the
non?overlap time of the gate drivers.
For the upper or control MOSFET, the power dissipation
dILo dt + D VLo Lo
(16)
can be approximated from:
Current changes slowly in the input inductor so the input
capacitors must initially deliver the vast majority of the
PD,CONTROL + (IRMS,CNTL2 @ RDS(on))
) (ILo,MAX @ Qswitch Ig @ VIN @ fSW)
(19)
input current. The amount of voltage drop across the input
capacitors ( ? V Ci ) is determined by the number of input
capacitors (N IN ), their per capacitor ESR (ESR IN ), and the
current in the output inductor according to:
) (Qoss 2 @ VIN @ fSW) ) (VIN @ QRR @ fSW)
The first term represents the conduction or IR losses when
the MOSFET is ON while the second term represents the
D VCi + ESRIN NIN @ dILo dt @ tON
+ ESRIN NIN @ dILo dt @ D fSW
(17)
switching losses. The third term is the losses associated with
the control and synchronous MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
Before the load is applied, the voltage across the input
inductor (V Li ) is very small ? the input capacitors charge to
the input voltage, V IN . After the load is applied the voltage
drop across the input capacitors, ? V Ci , appears across the
input inductor as well. Knowing this, the minimum value of
the input inductor can be calculated from:
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
Where I RMS,CNTL is the RMS value of the trapezoidal
current in the control MOSFET:
LiMIN + VLi
+ D VCi
dIIN dtMAX
dIIN dtMAX
(18)
IRMS,CNTL + [D @ (ILo,MAX2 ) ILo,MAX @ ILo,MIN (20)
) ILo,MIN2) 3]1 2
dI IN /dt MAX is the maximum allowable input current slew
I Lo,MAX is the maximum output inductor current:
rate.
The input inductance value calculated from Equation 18
is relatively conservative. It assumes the supply voltage is
very “stiff” and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
values of the capacitors specified by the manufacturer’s data
sheets are worst case high limits. In reality input voltage
“sag,” lower capacitor ESRs, and stray inductance will help
ILo,MAX + IO,MAX 2 ) D ILo 2
I Lo,MIN is the minimum output inductor current:
ILo,MIN + IO,MAX 2 * D ILo 2
I O,MAX is the maximum converter output current.
D is the duty cycle of the converter:
D + VOUT VIN
(21)
(22)
(23)
reduce the slew rate of the input current.
As with the output inductor, the input inductor must
support the maximum current without saturating the
? I Lo is the peak?to?peak ripple current in the output
inductor of value Lo:
magnetic. Also, for an inexpensive iron powder core, such
as the ?26 or ?52 from Micrometals, the inductance “swing”
D ILo + (VIN * VOUT) @ D (Lo @ fSW)
(24)
with DC bias must be taken into account ? inductance will
decrease as the DC input current increases. At the maximum
input current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
5. MOSFET & Heatsink Selection
R DS(on) is the ON resistance of the MOSFET at the
applied gate drive voltage.
Q switch is the post gate threshold portion of the
gate?to?source charge plus the gate?to?drain charge. This
may be specified in the data sheet or approximated from the
gate?charge curve as shown in the Figure 17.
Power dissipation, package size, and thermal solution
drive MOSFET selection. To adequately size the heat sink,
the design must first predict the MOSFET power dissipation.
http://onsemi.com
20
Qswitch + Qgs2 ) Qgd
(25)
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