参数资料
| 型号： | NCP5332ADWR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/30页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK 2PH STEPDWN 28SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 1 |
| 应用： | 控制器，高性能处理器 |
| 输入电压： | 4.5 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5332ADWR2OSCT |
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NCP5332A
transition between fast and slow positioning is controlled by
the total ramp size and the error amp compensation. If the
current signal size is too large or the error amp too slow there
will be a long transition to the final voltage after a transient.
This will be most apparent with lower capacitance output
filters.
Error Amp Compensation & Tuning
The transconductance error amplifier requires a capacitor
(C CMP1 in the Applications Diagram) between the COMP
pin and GND. This capacitor stabilizes the transconductance
error amplifier. Values less than 1 nF may cause oscillations
of the COMP voltage. These oscillations will increase the
output voltage jitter.
The capacitor (C AMP ) between the COMP pin and the
inverting error amplifier input (the V FB pin) and the parallel
combination of the resistors R FBK1 and R DRP1 determine the
bandwidth of the error amplifier. The gain of the error
amplifier crosses 0 dB at a high enough frequency to give a
quick transient response, but well below the switching
frequency to minimize ripple and noise on the COMP pin.
A capacitor in parallel with the V FB resistor (C FBK2 ) adds
a zero to boost phase near the crossover frequency to
improve loop stability.
Setting?up and tuning the error amplifier is a three step
process. First, the no?load and full?load adaptive voltage
positioning (AVP) are set using R FBK1 and R DRP1 ,
respectively. Second, the current sense time constant and
error amplifier gain are adjusted with R CSn and C AMP while
monitoring V OUT during transient loading. Lastly, the
peak?to?peak voltage ripple on the COMP pin is examined
when the converter is fully loaded to insure low output
voltage jitter. The details of this process are covered in the
Design Procedure section.
Undervoltage Lockout (UVLO)
The controller has undervoltage lockout functions
connected to two pins. One, intended for the logic and
low?side drivers, with approximately a 4.2 V turn?on
threshold is connected to the V CCL pin. A second, for the
high side drivers, with approximately a 9.0 V threshold, is
connected to the V CCH1 pin.
The UVLO threshold for the high side drivers varies with
the part type. In many applications this function will be
disabled or will only check that the applicable supply is on
? not that is at a high enough voltage to run the converter. See
individual datasheets for more information on UVLO.
Soft Start Enable, and Hiccup Mode
A capacitor between the Soft Start pin and GND controls
Soft Start and Hiccup mode slopes. A 0.1 μ F capacitor with
the 30 μ A charge current will allow the output to ramp up at
0.3 V/ms or 1.6 V in 5.3 ms at start?up.
When a fault is detected due to an overcurrent condition
the converter will enter a low duty cycle hiccup mode.
During hiccup mode the converter will not switch from the
time a fault is detected until the Soft Start capacitor has
discharged below the Soft Start Discharge Threshold and
then charged back up above the Channel Start Up Offset.
The Soft Start pin will disable the converter when pulled
below the maximum Soft Start Discharge Threshold
(nominally 0.27 V).
Power Good (PWRGD)
The open?collector Power Good (PWRGD) pin is driven
by a “window?comparator” monitoring V CORE . If V CORE is
greater than ?14% of the nominal VID setting and less than
2.0 V, this comparator will transition LOW causing
PWRGD to go HIGH. If V CORE falls below 14% or rises
above 2.0 V, the comparator will transition high and after a
120 μ s delay, PWRGD will be pulled low.
Layout Guidelines
With the fast rise, high output currents of microprocessor
applications, parasitic inductance and resistance should be
considered when laying out the power, filter and feedback
signal sections of the board. Typically, a multi?layer board
with at least one ground plane is recommended. If the layout
is such that high currents can exist in the ground plane
underneath the controller or control circuitry, the ground
plane can be slotted to route the currents away from the
controller. The slots should typically not be placed between
the controller and the output voltage or in the return path of
the gate drive. Additional power and ground planes or
islands can be added as required for a particular layout.
Gate drives experience high di/dt during switching and the
inductance of gate drive traces should be minimized. Gate
drive traces should be kept as short and wide as practical and
should have a return path directly below the gate trace.
Output filter components should be placed on wide planes
connected directly to the load to minimize resistive drops
during heavy loads and inductive drops and ringing during
transients. If required, the planes for the output voltage and
return can be interleaved to minimize inductance between
the filter and load.
The current sense signals are typically tens of milli?volts.
Noise pick?up should be avoided wherever possible.
Current feedback traces should be routed away from noisy
areas such as the switch node and gate drive signals. If the
current signals are taken from a location other than directly
at the inductor any additional resistance between the
pick?off point and the inductor appears as part of the
inherent inductor resistances and should be considered in
design calculations. The capacitors for the current feedback
networks should be placed as close to the current sense pins
as practical. After placing the NCP5332A control IC, follow
these guidelines to optimize the layout and routing:
1. Place the 1 μ F power supply bypass (ceramic)
capacitors close to their associated pins: V CCL ,
V CCH1 (and/or V CCH2 ), V CCL1 (and/or V CCL2 ).
2. Place the MOSFETs to minimize the length of the
Gate traces. Orient the MOSFETs such that the
Drain connections are away from the controller and
the Gate connections are closest to the controller.
http://onsemi.com
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