参数资料
| 型号： | NCP5332ADWR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 21/30页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK 2PH STEPDWN 28SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 1 |
| 应用： | 控制器，高性能处理器 |
| 输入电压： | 4.5 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5332ADWR2OSCT |
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NCP5332A
θ SA is the sink?to?ambient thermal impedance of the
V GS_TH
I D
V GATE
heatsink assuming direct mounting of the MOSFET (no
thermal “pad” is used).
T J is the specified maximum allowed junction
temperature.
T A is the worst case ambient operating temperature.
For TO?220 and TO?263 packages, standard FR?4
copper clad circuit boards will have approximate thermal
resistances ( θ SA ) as shown below:
Pad Size
Single?Sided
Q GS1
Q GS2
Q GD
V DRAIN
(in 2 /mm 2 )
1 oz. Copper
0.5/323
60?65 ° C/W
Figure 17. MOSFET Switching Characteristics
I g is the output current from the gate driver IC.
V IN is the input voltage to the converter.
f sw is the switching frequency of the converter.
Q G is the MOSFET total gate charge to obtain R DS(on) .
Commonly specified in the data sheet.
0.75/484
1.0/645
1.5/968
2.0/1290
2.5/1612
55?60 ° C/W
50?55 ° C/W
45?50 ° C/W
38?42 ° C/W
33?37 ° C/W
V g is the gate drive voltage.
Q RR is the reverse recovery charge of the lower MOSFET.
Q oss is the MOSFET output charge specified in the data
sheet.
For the lower or synchronous MOSFET, the power
dissipation can be approximated from:
As with any power design, proper laboratory testing
should be performed to insure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow,
maximum input voltage, maximum loading, and component
PD,SYNCH + (IRMS,SYNCH2 @ RDS(on))
) (Vfdiode @ IO,MAX 2 @ t_nonoverlap @ fSW)
(26)
variations (i.e. worst case MOSFET R DS(on) ). Also, the
inductors and capacitors share the MOSFET’s heatsinks and
will add heat and raise the temperature of the circuit board
IRMS,SYNCH + [(1 * D)
q T t (TJ * TA) PD
The first term represents the conduction or IR losses when
the MOSFET is ON and the second term represents the diode
losses that occur during the gate non?overlap time.
All terms were defined in the previous discussion for the
control MOSFET with the exception of:
(27)
@ (ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2
where:
Vf diode is the forward voltage of the MOSFET’s intrinsic
diode at the converter output current.
t_nonoverlap is the non?overlap time between the upper
and lower gate drivers to prevent cross conduction. This
time is usually specified in the data sheet for the control
IC.
When the MOSFET power dissipations are known, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature
(28)
where;
θ T is the total thermal impedance ( θ JC + θ SA ).
θ JC is the junction?to?case thermal impedance of the
MOSFET.
and MOSFET. For any new design, its advisable to have as
much heatsink area as possible – all too often new designs
are found to be too hot and require re?design to add
heatsinking.
6. Adaptive Voltage Positioning
There are two resistors that determine the Adaptive
Voltage Positioning: R VFBK and R DRP . R VFBK establishes
the no?load “high” voltage position and R DRP determines
the full?load “droop” voltage.
Resistor R VFBK is connected between V CORE and the V FB
pin of the controller. At no load, this resistor will conduct the
internal bias current of the V FB pin and develop a voltage
drop from V CORE to the V FB pin. Because the error amplifier
regulates V FB to the DAC setting, the output voltage,
V CORE , will be lower by the amount IBIAS VFB ? R VFBK .
This condition is shown in Figure 18.
To calculate R VFBK the designer must specify the no?load
voltage decrease below the VID setting ( ? V NO?LOAD ) and
determine the V FB bias current. Usually, the no?load voltage
decrease is specified in the design guide for the processor
that is available from the manufacturer. It is a voltage that,
under load transient condition, will be the maximum
acceptable for the VID code setting. The V FB bias current is
determined by the value of the resistor from R OSC to ground
(see Figure 5 in the data sheet for a graph of IBIAS VFB
versus R OSC ). The value of R VFBK can then be calculated:
http://onsemi.com
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