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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
REV 1.1 June, 2000
19
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Clock Enable (CKE) Truth Table
CKE
Command
Current
State
Previous
Cycle
Current
Cycle
/CS
/RAS
/CAS
/WE
A12,
A13
A11–
A10
Action
Notes
H
X
INVALID
1
L
H
X
Exit Self Refresh with
Device Deselect
2
L
H
L
H
X
Exit Self Refresh with No
Operation
2
L
H
L
H
L
X
ILLEGAL
2
L
H
L
H
L
X
ILLEGAL
2
L
H
L
X
ILLEGAL
2
Self
Fresh
L
X
Maintain Self Refresh
H
X
INVALID
1
L
H
X
Power Down mode exit,
all banks idle
2
L
H
L
X
ILLEGAL
2
Power
Down
L
X
Maintain Power Down
Mode
H
X
3
H
L
H
X
3
H
L
H
X
Refer to the Idle State
section of the Current
State Truth Table
3
H
L
H
X
CBR Refresh
H
L
OP Code
Mode Register Set
4
H
L
H
X
3
H
L
H
X
3
H
L
H
X
Refer to the Idle State
section of the Current
State Truth Table
3
H
L
H
X
Entry Self Refresh
4
H
L
OP Code
Mode Register Set
All
Banks
Idle
L
X
Power Down
4
H
X
Refer to operations in the
Current State Truth Table
H
L
X
Begin Clock Suspend
next cycle
5
L
H
X
Exit Clock Suspend next
cycle
Any
State
other
than
listed
above
L
X
Maintain Clock Suspend
1.
For the given Current State CKE must be low in the previous cycle.
2.
When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for
CKE (tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on
the first rising clock after CKE goes high .
3.
The address inputs (A13 - A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table
for more information.
4.
The Precharge Power Down Mode,the Self Refresh Mode,and the Mode Register Set can only be entered from the all banks idle
state.
5.
Must be a legal command as defined in the Current State Truth Table.