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参数资料
| 型号： | NT56V6620C0T-75 |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM, PDSO54 |
| 封装： | 0.400 INCH, SSOP2-54 |
| 文件页数： | 13/66页 |
| 文件大小： | 1701K |
| 代理商： | NT56V6620C0T-75 |
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
REV 1.1 June, 2000
20
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Current State Truth Table (Part 1 of 3)(See note 1)
Command
Current
State
/CS
/RAS
/CAS
/WE
A12,
A13
A11-A0
Description
Action
Notes
L
OP Code
Mode Register Set
Set the Mode Register
2
L
H
X
Auto or Self Refresh
Start Auto or Self Refresh
2,3
L
H
L
BS
X
Precharge
No Operation
L
H
BS
Row
Address
Bank Active
Activate the specified bank
and row
L
H
L
BS
Column
Write
ILLEGAL
4
L
H
L
H
BS
Column
Read
ILLEGAL
4
L
H
L
X
Burst Termination
No Operation
L
H
X
No Operation
Idle
H
X
Device Deselect
No Operation or Power Down
5
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
BS
X
Precharge
6
L
H
BS
Row
Address
Bank Active
ILLEGAL
4
L
H
L
BS
Column
Write
Start Write; Determine if Auto
Precharge
7,8
L
H
L
H
BS
Column
Read
Start Read; Determine if Auto
Precharge
7,8
L
H
L
X
Burst Termination
No Operation
L
H
X
No Operation
Row
Active
H
X
Device Deselect
No Operation
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
BS
X
Precharge
Terminate Burst; Start the
Precharge
L
H
BS
Row
Address
Bank Active
ILLEGAL
4
L
H
L
BS
Column
Write
Terminate Burst; Start the
Write cycle
8,9
L
H
L
H
BS
Column
Read
Terminate Burst; Start a new
Read cycle
8,9
L
H
L
X
Burst Termination
Terminate the Burst
L
H
X
No Operation
Continue the Burst
Read
H
X
Device Deselect
Continue the Burst
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto or Self Refresh
ILLEGAL
L
H
L
BS
X
Precharge
Terminate Burst; Start the
Precharge
L
H
BS
Row
Address
Bank Active
ILLEGAL
4
L
H
L
BS
Column
Write
Terminate Burst; Start a new
Write cycle
8,9
L
H
L
H
BS
Column
Read
Terminate Burst; Start the
Read cycle
8,9
L
H
L
X
Burst Termination
Terminate the Burst
L
H
X
No Operation
Continue the Burst
Write
H
X
Device Deselect
Continue the Burst
1.
CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the
Command is being applied to.
2.
All Banks must be idle; otherwise, it is an illegal action.
3.
If CKE is active (high) the SDRAM will start the Auto(CBR) Refresh operation, if CKE is inactive(low) than the Self Refresh mode is
entered.
4.
The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being
referenced by the Current State then the action may be legal depending on the state of that bank.
5.
If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6.
The minimum and maximum Active time (tRAS) must be satisfied.
7.
The RAS to CAS Delay (tRCD) must occur before the command is given.
8.
Column address A10 is used to determine if the Auto Precharge function is activated.
9.
The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
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