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参数资料
| 型号： | NT56V6620C0T-75 |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM, PDSO54 |
| 封装： | 0.400 INCH, SSOP2-54 |
| 文件页数： | 16/66页 |
| 文件大小： | 1701K |
| 代理商： | NT56V6620C0T-75 |
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
REV 1.1 June, 2000
23
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
1.
CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the
Command is being applied to.
2.
All Banks must be idle; otherwise, it is an illegal action.
3.
If CKE is active (high) the SDRAM will start the Auto(CBR) Refresh operation, if CKE is inactive(low) than the Self Refresh mode is
entered.
4.
The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being
referenced by the Current State then the action may be legal depending on the state of that bank.
5.
If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6.
The minimum and maximum Active time (tRAS) must be satisfied.
7.
The RAS to CAS Delay (tRCD) must occur before the command is given.
8.
Column address A10 is used to determine if the Auto Precharge function is activated.
9.
The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
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