NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
REV 1.1 June, 2000
16
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Mode Register Set Cycle
- 7
- 75B
- 75
- 8B
- 8A
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Note
tRSC
Mode Register Set
Cycle Time
2
-
2
-
2
-
2
-
2
-
CLK
1
1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of
clock cycles = specified value of timing / clock period (count fractions as a whole number).
Read Cycle
- 7
- 75B
- 75
- 8B
- 8A
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Note
2.5
-
2.5
-
2.5
-
ns
1
tOH
Data Out Hold Time
2.7
-
2.7
-
3
-
3
-
ns
2
tLZ
Data Out to Low Impedance
Time
0
-
0
-
0
-
0
-
0
-
ns
tHZ3
3
6
3
5.4
3
5.4
3
6
3
6
ns
3
tHZ2
Data Out to High
Impedance Time
-
3
6
3
8
ns
3
tDQZ
DQM Data Out Disable
Latency
2
-
2
-
2
-
2
-
2
-
CLK
1.AC Output Load Circuit A.
2.AC Output Load Circuit B.
3.Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Refresh Cycle
- 7
- 75B
- 75
- 8B
- 8A
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Note
tREF
Refresh Period
-
64
-
64
-
64
-
64
-
64
ms
tSREX
Self Refresh Exit Time
10
-
10
-
10
-
10
-
10
-
ns
Write Cycle
- 7
- 75B
- 75
- 8B
- 8A
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Note
tDS
Data In Set-up Time
2
-
1.5
-
1.5
-
2
-
2
-
ns
tDH
Data In Hold Time
1
-
0.8
-
0.8
-
1
-
1
-
ns
tDPL
Data input to Precharge
14
-
15
-
15
-
15
-
15
-
ns
tDAL3
Data In to Active Delay
/CAS Latency = 3
5
-
5
-
5
-
5
-
5
-
CLK
tDAL2
Data In to Active Delay
/CAS Latency = 2
-
4
-
3
-
CLK
tDQW
DQM Write Mask Latency
0
-
0
-
0
-
0
-
0
-
ns