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参数资料
| 型号： | NT56V6620C0T-75 |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM, PDSO54 |
| 封装： | 0.400 INCH, SSOP2-54 |
| 文件页数： | 18/66页 |
| 文件大小： | 1701K |
| 代理商： | NT56V6620C0T-75 |
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
REV 1.1 June, 2000
25
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Mode Register Definition
Mode Register set: (Programming mode)
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address bus
(Ax)
Operation Mode
CAS Latency
BT
Burst Length
Mode Register
(Mx)
CAS Latency
Burst Type
Burst Length
M6
M5
M4
Latency
M3
Type
M2
M1
M0
BT=0
BT=1
0
Reserved
0
Sequential
0
1
0
1
Reserved
1
Interleave
0
1
2
0
1
0
2
0
1
0
4
0
1
3
0
1
8
1
0
Reserved
1
0
Reserved
1
0
1
Reserved
1
0
1
Reserved
1
0
Reserved
1
0
Reserved
1
Reserved
1
Full Page
Reserved
Operation Mode
M13
M12
M11
M10
M9
M8
M7
Mode
0
Normal
0
1
0
Multiple Burst with Single Write
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle).
Three parameters define how the burst mode will operate: burst sequence, burst length, and operation mode. The burst sequence and burst
length are programmable and are determined by address bits A0 - A3 during the Mode Register Set command. Operation mode is also
programmable and is set by address bits A7 - A13.
Burst sequence defines the order in which the burst data will be delivered or stored to the SDRAM. The two types of burst sequence
supported are sequential and interleaved. See the table below.
The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a Write
Command. The burst length can be programmed to have values of 1, 2, 4, 8 or full page (actual page length is dependent on organization:
x4, x8, or x16). Full page burst operation is only possible using the sequential burst type.
Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the device will
perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with single write operation
was added to support Write Through Cache operation. Here, the programmed burst length only applies to read cycles. All write cycles are
single write operations when this mode is selected.
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