参数资料
型号: NT5SV8M16FT-75BI
厂商: NANYA TECHNOLOGY CORP
元件分类: DRAM
英文描述: 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封装: 0.400 MM, PLASTIC, TSSOP2-54
文件页数: 20/65页
文件大小: 739K
代理商: NT5SV8M16FT-75BI
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.4
08/2009
27
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Data Mask
The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is
activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is
activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock delay, independent
of CAS latency.
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state. The purpose of the No
Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Com-
mand will not terminate a previous operation that is still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is
brought high, the RAS, CAS, and WE signals become don’t cares.
Data Mask Activated during a Read Cycle
COMMAND
NOP
READ A
NOP
DQM
: “H” or “L”
A two-clock delay before
the DQs become Hi-Z
DQs
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
DOUT A0
DOUT A1
(Burst Length = 4, CAS Latency = 2)
相关PDF资料
PDF描述
NT5TU64M16DG-3C 64M X 16 DDR DRAM, 0.45 ns, PBGA84
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
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