参数资料
型号: NT5SV8M16FT-75BI
厂商: NANYA TECHNOLOGY CORP
元件分类: DRAM
英文描述: 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封装: 0.400 MM, PLASTIC, TSSOP2-54
文件页数: 6/65页
文件大小: 739K
代理商: NT5SV8M16FT-75BI
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.4
08/2009
14
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Burst Write Command
The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock.
The address inputs determine the starting column address. There is no CAS latency required for burst write cycles. Data for the
first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining
data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has fin-
ished, any additional data supplied to the DQ pins will be ignored.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is inter-
rupted, the remaining addresses are overridden by the new address and data will be written into the device until the pro-
grammed burst length is satisfied.
Burst Write Operation
Write Interrupted by a Write
COMMAND
NOP
WRITE A
NOP
DQs
DIN A0
DIN A1
DIN A2
DIN A3
NOP
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Extra data is masked.
The first data element and the Write
are registered on the same clock edge.
(Burst Length = 4, CAS latency = 2, 3)
: “H” or “L”
COMMAND
NOP
WRITE A
WRITE B
NOP
DQs
DIN A0
DIN B0
DIN B1
DIN B2
NOP
DIN B3
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
1 CK Interval
(Burst Length = 4, CAS latency = 2, 3)
相关PDF资料
PDF描述
NT5TU64M16DG-3C 64M X 16 DDR DRAM, 0.45 ns, PBGA84
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
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