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参数资料
| 型号： | NT5SV8M16FT-75BI |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封装： | 0.400 MM, PLASTIC, TSSOP2-54 |
| 文件页数： | 34/65页 |
| 文件大小： | 739K |
| 代理商： | NT5SV8M16FT-75BI |
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NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.4
08/2009
4
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Pin Description
CK
Clock Input
DQ0-DQ15
Data Input/Output
CKE (CKE0, CKE1)
Clock Enable
DQM, LDQM, UDQM
Data Mask
CS
Chip Select
VDD
Power (+3.3V)
RAS
Row Address Strobe
VSS
Ground
CAS
Column Address Strobe
VDDQ
Power for DQs (+3.3V)
WE
Write Enable
VSSQ
Ground for DQs
BA1, BA0
Bank Select
NC
No Connection
A0 - A11
Address Inputs
—
Input/Output Functional Description
Symbol
Type
Polarity
Function
CK
Input
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
CKE, CKE0,
CKE1
Input
Active High
Activates the CK signal when high and deactivates the CK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CS
Input
Active Low
CS enables the command decoder when low and disables the command decoder when high. When
the command decoder is disabled, new commands are ignored but previous operations continue.
RAS, CAS, WE
Input
Active Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be
executed by the SDRAM.
BA1, BA0
Input
—
Selects which bank is to be active.
A0 - A11
Input
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sam-
pled at the rising clock edge.
During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8), when sam-
pled at the rising clock edge.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is
high, auto-precharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BA0, BA1 to control which
bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10
is low, then BA0 and BA1 are used to define which bank to precharge.
DQ0 - DQ15
Input-
Output
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DQM
LDQM
UDQM
Input
Active High
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In
x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In
Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output
enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has
a latency of zero and operates as a word mask by allowing input data to be written if it is low but
blocks the write operation if DQM is high.
VDD, VSS
Supply
—
Power and ground for the input buffers and the core logic.
VDDQ VSSQ
Supply
—
Isolated power supply and ground for the output buffers to provide improved noise immunity.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5SV8M16HS-6K | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5SV8M8DT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mb Synchronous DRAM |
| NT5SV8M8DT-6K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mb Synchronous DRAM |
| NT5SV8M8DT-7 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mb Synchronous DRAM |
| NT5SV8M8DT-7K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mb Synchronous DRAM |
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