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参数资料
| 型号： | NT5SV8M16FT-75BI |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封装： | 0.400 MM, PLASTIC, TSSOP2-54 |
| 文件页数： | 9/65页 |
| 文件大小： | 739K |
| 代理商： | NT5SV8M16FT-75BI |
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NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.4
08/2009
17
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command
or the auto-precharge function. When a Read or a Write Command is given to the SDRAM, the CAS timing accepts one extra
address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during
the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst opera-
tion is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write
Command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute as
normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed.
Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last data output. Auto-precharge can
also be implemented during Write commands.
A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or
Write Command with auto-precharge cannot be interrupted by a command to the same bank. Therefore use of a Read, Write, or
Precharge Command to the same bank is prohibited during a read or write cycle with auto-precharge until the entire burst oper-
ation is completed. Once the precharge operation has started the bank cannot be reactivated until the Precharge time (tRP) has
been satisfied.
When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal
precharge operation must satisfy tRAS(min). If this interval does not satisfy tRAS(min) then tRCD must be extended.
Burst Read with Auto-Precharge
COMMAND
NOP
READ A
Auto-Precharge
tRP
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
tRP
*
tCK2, DQs
CAS latency = 2
tCK3, DQs
CAS latency = 3
Begin Auto-precharge
*Bank can be reactivated at completion of tRP.
DOUT A0
NOP
tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
(Burst Length = 1, CAS Latency = 2, 3)
相关PDF资料 |
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| NT5TU64M16DG-3C | 64M X 16 DDR DRAM, 0.45 ns, PBGA84 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5SV8M16HS-6K | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5SV8M8DT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mb Synchronous DRAM |
| NT5SV8M8DT-6K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mb Synchronous DRAM |
| NT5SV8M8DT-7 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mb Synchronous DRAM |
| NT5SV8M8DT-7K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mb Synchronous DRAM |
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