ORSO42G5-3BMN484C (Lattice) PDF资料下载 Datasheet(102/153 页)

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型号：	ORSO42G5-3BMN484C
厂商：	Lattice Semiconductor Corporation
文件页数：	102/153页
文件大小：	0K
描述：	IC TRANCEIVERS FPSC 680FPGAM
产品变化通告：	Product Discontinuation 01/Aug/2011
标准包装：	60
系列：	*

Lattice Semiconductor

ORCA ORSO42G5 and ORSO82G5 Data Sheet

There is no way to tell where a cell starts unless one counts the cells from the beginning of the SPE. That means,

there is no way to regain lost cell delineation other than wait for the next SONET frame.

Cell Mode Transmit Path

In the transmit path in cell mode, the transmit logic creates a SONET-like transport frame for the data, adds the

required Transport OverHead bytes (cell mode automatically uses AUTO_TOH mode) and retimes the cell data

from the FPGA interface rate of 156 MHz to the framer rate of 77.76 MHz. The data are then sent to the SONET

logic blocks and SERDES. The Payload sub-block of the SONET logic operates somewhat differently than in

SONET mode, however.

Output Port Controller

The ORSO42G5 has two link controllers (OPC2s). In cell mode the Output Port Controller (OPC) is the block

responsible for directing trafc for the transmit trafc ow. There are four two-link controllers and one eight-link con-

troller (OPC8) in the ORSO82G5. The user provides 160-bit data (OPC8) or 40-bit data (OPC2s) at 156 MHz,

along with a cell valid strobe from the FPGA logic. No Link Header byte is sent with the cell data. The OPC provides

the following functions:

Accepts cell payload from the FPGA logic and assembles legal output cells from these.

Inserts Bit Interleaved Parity (BIP)

Schedules, manages and performs writes of cell data into TX FIFOs in the transmit framer blocks of all the eight-

links or up to 4 pairs of two-links.

Provides backpressure information to the FPGA to stop writes to the TXFIFO if the FIFO is not ready to accept

data.

The OPC blocks, shown in Figure 39, operate as follows:

OPC8 to stripe cells across eight links (ORSO82G5 only)

OPC2_A1 to service links AA,AB (ORSO82G5 only)

OPC2_A2 to service links AC,AD

OPC2_B1 to service links BA,BB (ORSO82G5 only)

OPC2_B2 to service links BC,BD

When operating with some links in the two-link cell mode, links not in an alignment group can optionally be oper-

ated in SONET and/or SERDES-only modes.

相关代理商/技术参数	参数描述
ORSO42G5-EV	功能描述:可编程逻辑 IC 开发工具 Eval Brd ORSO42G5 RoHS:否制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:
ORSO82G5	制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C	功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1BM680I	功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1F680C	功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256

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