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参数资料
型号： ORSO42G5-3BMN484C
厂商： Lattice Semiconductor Corporation
文件页数： 137/153页
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
产品变化通告： Product Discontinuation 01/Aug/2011
标准包装： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
84
30824 - AC
30834 - AD
30924 - BC
30934 - BD
[0]
LCKREFN_xx
00
0 = Lock receiver to reference clock (REFCLK)
1 = Lock receiver to HDINxx data
Both
[1]
LOOPENB_xx
LOOPENB_xx =1 Enable high-speed internal
loopback from TX to RX. Disable the HDOUT
buffers.
Both
[2]
DISABLE_TX_xx
Disable Transmitter, For DISABLE_TX = 1 the
TX Link is disabled. The disabled link is ignored
by the Output Port Controller (OPC) and inter-
nally generated idle cells are transmitted on the
link.fIf the link is disabled during the transmis-
sion of a cell on the link, the entire cell is trans-
mitted before the link is declared invalid.
Cell
[3]
DISABLE_RX_xx
Disable Receiver, DISABLE_RX = 1 disables
the RX link for cell processing by the Input Port
Controller (IPC). The IPC will not read cells from
a link if this bit is set for that link
Cell
[4]
CELL_BIP_INH_xx
Cell BIP (Check) Inhibit, CELL_BIP_INH = 1
prevents cells from being dropped due to a Cell
BIP error, in the RX path. If this bit is not set,
then cells will be dropped automatically if a cell
bip error is detected by the core. The CELL-
DROP signal across the core-FPGA interface
will be active only if this bit is NOT set.
Cell
[5]
CELL_SEQ_INH_xx
Cell Sequence (Checking) Inhibit,
CELL_SEQ_INH = 1 prevents cells in the RX
path from being dropped due to a sequence
error. If this bit is not set, then cells will be
dropped automatically if a sequence error is
detected internally. The CELLDROP signal
across the core-FPGA interface will be active
only if this bit is NOT set.
Cell
[6]
AUTO_TOH_xx
Automatic TOH Generation, AUTO_TOH_xx =1
enables the TX core to automatically generate
TOH bytes. All the FORCE_* register bits are
valid if this bit is set. This bit should be set to 1
in Cell Mode. It can be set to 1or 0 in SONET
Mode. If this bit is not set, then user has to pro-
vide all the TOH bytes or use the AUTO_SOH
mode.
SONET
[7]
FMPU_RESYNC1_xx
Single channel alignment FIFO reset. Rising
edge sensitive. Write a 0 and then a 1 to enable
this bit. When enabled, the read pointer in the
alignment FIFO is reset to the middle of the
FIFO. This bit is valid only when
FMPU_SYNMODE_xx = 00 (no multi channel
alignment)
SONET
30825 - AC
30835 - AD
30925 - BC
30935 - BD
[0:7]
LINK_NUM_TX_xx
00
Transmit Link Number, This value is transmitted
in the “F1” byte of the TOH. This value is used to
verify that the links are connected properly and
is only used in the AUTO_TOH mode.
Both
Table 26. Per-Channel Control Register Descriptions – ORSO42G5 (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
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相关代理商/技术参数
参数描述
ORSO42G5-EV 功能描述:可编程逻辑 IC 开发工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:
ORSO82G5 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1BM680I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1F680C 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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