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参数资料
型号： ORSO42G5-3BMN484C
厂商： Lattice Semiconductor Corporation
文件页数： 115/153页
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
产品变化通告： Product Discontinuation 01/Aug/2011
标准包装： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
64
Signal Description for RX Path (SERDES Core to FPGA) – ORSO82G5
Signals are divided across 8 channels with 40 signals per channel. RXDxx[39:0] is the set of 40 signals for a
channel xx.
All RX direction signals are outputs from the core.
See Figure 47 for clock transfers across the FPGA/Core interface.
In SONET mode, RXDxx[31:0] carries 32 bit data from the alignment FIFO of the respective channel.
RXDxx[35:32] carries miscellaneous information such as OOF, BIPERR, Frame Pulse (FP), and SPE.
In cell mode, data from each of the four 2-link IPC bundles are spread across all eight channels and are assigned
to the 20 LSBs (RXDxx[19:0]) of each channel output. Data from IPC2_A1 is distributed across RXDAA[19:0]
and RXDAB[19:0]. Data from IPC2_A2 is distributed across RXDAC[19:0] and RXDAD[19:0]. This symmetry is
maintained for IPC2 data signals from block B.
Data from the 8-link IPC block IPC8 is spread across all eight channels and assigned to the 20 LSB’s
(RXDxx[19:0] of each channel output.
The IPC status signals for Cell Mode operation are contained in RXDxx[39:36] and RXDxx[33].
The signals for SONET Mode operation are assigned to RXDxx[35:34] and RXDxx[33].
Note that RXDxx[39:32] signal assignments are the same no matter what mode the RX blocks are in.
Table 14 summarizes the signals across the Core/FPGA interface in the receive direction.
33
—
32
DOUTBD_B1_ERR
[31:20]
DOUTBD[31:20]
—
[19:0]
DOUTBD[19:0]
IPC2_B2[19:0]
Table 14. RX Core/FPGA Interface Signals – ORSO82G5
RXDAA[39:0]
SONET mode
IPC2 A1 Mode
IPC8 Mode
39
SYNC2_A1_OOS
—
38
—
IPC2_A1_CELLDROP
—
37
—
IPC2_A1_CELLSTART
—
36
DOUTAA_FP
—
35
DOUTAA_OOF
34
DOUTAA_SPE
—
33
—
IPC2_A1_CELL_BIP_ERR
—
32
DOUTAA_B1_ERR
[31:20]
DOUTAA[31:20]
—
[19:0]
DOUTAA[19:0]
IPC2_A1[39:20]
—
RXDAB[39:0]
SONET mode
IPC2 A1 Mode
IPC8 Mode
39
—
38
SYNC4_A_OOS
—
37
—
CELL_BEGIN_OK_A1
—
36
DOUTAB_FP
—
35
DOUTAB_OOF
34
DOUTAB_SPE
—
Table 13. RX Core/FPGA Interface Signals – ORSO42G5 (Continued)
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