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参数资料
型号： ORSO42G5-3BMN484C
厂商： Lattice Semiconductor Corporation
文件页数： 122/153页
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
产品变化通告： Product Discontinuation 01/Aug/2011
标准包装： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
70
Toggle SOFT_RESET once all clocks have stabilized
– 30A06
01
– 30A06
00
3. SONET Alignment FIFO Resynchronization – ORSO42G5
If during operation a link goes OOF the alignment group will continue to run without the errored channel. To realign
this link with the rest of group once the OOF condition is cleared the group may need to be resynchronized. This
operation (for 4 channel alignment in block A) is shown below.
Toggle the FMPU_RESYNC2_A2 register bit to reset the alignment FIFO group.
– 30A04
04
– 30A04
00
This sequence will stop trafc temporarily on all links in the alignment grouping.
4. Two-Link Cell Mode Initialization – ORSO42G5
This sample initialization uses 2-link cell mode on all links (A1, A2, B1, and B2). Auto_Bundle and Auto_Remove
are both used for these links. The GSWRST_[A:B] Rejoin method is used.
Set SERDES PLL to Lock to Data signal and Auto_TOH mode (per channel, all channels)
– 30824 and 30834
82
Enable Auto_Remove and Rejoin
– 30A03
1B
Set 2-link cell mode for groups A2 and B2
– 30A05
0A
Toggle SOFT_RESET
– 30A06
01
– 30A06
00
Set the TX_CFG_DONE bit to indicate the transmitter is completely congured
– 30A07
01
Toggle GSWRST_[A:B] to clear the RX FIFOs
– 30005
20
– 30105
20
– 30005
00
– 30105
00
Turn Off Rejoin (clear the Rejoin register bits) and enable Auto_Bundle
– 30A03
49
Sample Initialization Sequences – ORSO82G5
The following paragraphs show sample control register write sequences for initialization and resynchronization for
the major modes of the device. Hexadecimal values will be shown for the data to be written into the control regis-
ters. For these values bit 0 will be the MSb while bit 7 is the LSb. For the per-channel control registers, only the rst
register address is shown. The other per-channel control registers must also be initialized for the desired mode.
1. SERDES-Only Mode Initialization – ORSO82G5
Set SERDES Only mode (per channel, channel AA selected for sample initialization)
– 30803
40
Set SERDES PLL to Lock to Data signal (per channel, channel AA selected for sample initialization)
– 30804
80
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ORSO42G5-EV 功能描述:可编程逻辑 IC 开发工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:
ORSO82G5 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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ORSO82G5-1F680C 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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