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参数资料
型号： P89V51RB2BBC,557
厂商： NXP Semiconductors
文件页数： 78/80页
文件大小： 0K
描述： IC 80C51 MCU 1024 RAM 44TQFP
产品培训模块： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装： 800
系列： 89V
核心处理器： 8051
芯体尺寸： 8-位
速度： 40MHz
连通性： SPI，UART/USART
外围设备： 欠压检测/复位，POR，PWM，WDT
输入/输出数： 32
程序存储器容量： 16KB（16K x 8）
程序存储器类型： 闪存
RAM 容量： 1K x 8
电压 - 电源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振荡器型： 内部
工作温度： 0°C ~ 70°C
封装/外壳： 44-TQFP
包装： 托盘
配用： 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
其它名称： 935277723557
P89V51RB2BBC
P89V51RB2BBC-ND
P89V51RB2_RC2_RD2_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 November 2009
8 of 80
NXP Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
P2.5/A13
26
23
29
I/O
P2.5 — Port 2 bit 5.
O
A13 — Address bit 13.
P2.6/A14
27
24
30
I/O
P2.6 — Port 2 bit 6.
O
A14 — Address bit 14.
P2.7/A15
28
25
31
I/O
P2.7 — Port 2 bit 7.
O
A15 — Address bit 15.
P3.0 to P3.7
I/O with
internal
pull-up
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 3 pins are pulled HIGH by the internal
pull-ups when ‘1’s are written to them and can be used as
inputs in this state. As inputs, Port 3 pins that are
externally pulled LOW will source current (IIL) because of
the internal pull-ups. Port 3 also receives some control
signals and a partial of high-order address bits during the
external host mode programming and verication.
P3.0/RXD
10
5
11
I
P3.0 — Port 3 bit 0.
I
RXD — Serial input port.
P3.1/TXD
11
7
13
O
P3.1 — Port 3 bit 1.
O
TXD — Serial output port.
P3.2/INT0
12
8
14
I
P3.2 — Port 3 bit 2.
I
INT0 — External interrupt 0 input.
P3.3/INT1
13
9
15
I
P3.3 — Port 3 bit 3.
I
INT1 — External interrupt 1 input.
P3.4/T0
14
10
16
I/O
P3.4 — Port 3 bit 4.
I
T0 — External count input to Timer/counter 0.
P3.5/T1
15
11
17
I/O
P3.5 — Port 3 bit 5.
I
T1 — External count input to Timer/counter 1.
P3.6/WR
16
12
18
O
P3.6 — Port 3 bit 6.
O
WR — External data memory write strobe.
P3.7/RD
17
13
19
O
P3.7 — Port 3 bit 7.
O
RD — External data memory read strobe.
PSEN
29
26
32
I/O
Program Store Enable: PSEN is the read strobe for
external program memory. When the device is executing
from internal program memory, PSEN is inactive (HIGH).
When the device is executing code from external program
memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each
access to external data memory. A forced HIGH-to-LOW
input transition on the PSEN pin while the RST input is
continually held HIGH for more than 10 machine cycles will
cause the device to enter external host mode
programming.
Table 3.
P89V51RB2/RC2/RD2 pin description …continued
Symbol
Pin
Type
Description
DIP40
TQFP44
PLCC44
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