
QuadFALCTM
PEF 22554 E
E1 Registers
Data Sheet
390
Rev. 1.2, 2006-01-26
Receive Sa6-Bit Status
Four consecutive received Sa6-bits are checked on the by ETS300233 defined Sa6-bit combinations. The
QuadFALCTM detects the following “fixed” Sa6-bit combinations: SA61, SA62, SA63, SA64 = 1000B, 1010B, 1100B,
1110B, 1111B. All other possible 4-bit combinations are grouped to status “X”. A valid Sa6-bit combination must
occur three times in a row. The corresponding status bit in this register is set. Even if the detected status is active
for a short time the status bit remains active until this register is read. Reading the register resets all pending status
information. With any change of state of the Sa6-bit combinations an interrupt status ISR0.SA6SC is generated.
During the basic frame asynchronous state updating of this register and interrupt status ISR0.SA6SC is disabled.
In multiframe format the detection of the Sa6-bit combinations can be done either synchronous or asynchronous
to the submultiframe (FMR3.SA6SY). In synchronous detection mode updating of register RSA6S is done in the
multiframe synchronous state (FRS0.LMFA = 0B). In asynchronous detection mode updating is independent to the
multiframe synchronous state.
RSA6S_E
Offset
Reset Value
Receive Sa6-Bit Status
xx61H
xxH
Field
Bits
Type
Description
S_X
5
r
Receive Sa6-Bit Status_X
If none of the fixed Sa6-bit combinations are detected this bit is set.
S_F
4
r
Receive Sa6-Bit Status: "1111"
Receive Sa6-bit status “1111B” is detected for three times in a row in the
Sa6-bit positions.
S_E
3
r
Receive Sa6-Bit Status: "1110"
Receive Sa6-bit status “1110B” is detected for three times in a row in the
Sa6-bit positions.
S_C
2
r
Receive Sa6-Bit Status: "1100"
Receive Sa6-bit status “1100B” is detected for three times in a row in the
Sa6bit positions.
S_A
1
r
Receive Sa6-Bit Status: "1010"
Receive Sa6-bit status “1010B” is detected for three times in a row in the
Sa6-bit positions.
S_8
0
r
Receive Sa6-Bit Status: "1000"
Receive Sa6-bit status “1000B” is detected for three times in a row in the
Sa6-bit positions.