Data Sheet
101
Rev. 1.2, 2006-01-26
QuadFALC
TM
PEF 22554 E
Functional Description E1/T1/J1
IDCODE
A 32-bit identification register is serially read out on pin TDO. It contains the version number (4 bits), the device
code (16 bits) and the manufacturer code (11 bits). The LSB is fixed to 1
B.
The ID code field is set to (MSB to LSB): t.b.d.
Version number (first 4 bits) = 0001
B
Part Number (next 16 bits) = 00000001 00000100
B
Manufacturer ID (next 11 bits) = 00001000001
B
LSB fixed to 1
B.
BYPASS
A bit entering TDI is shifted to TDO after one TCK clock cycle.
An alphabetical overview of all TAP controller operation codes is given in Table 12.
3.4.6
Master Clocking Unit
The QuadFALC
TM provides a flexible clocking unit, which references to any clock in the range of 1.02 to 20 MHz
The clocking unit has two different modes:
In the “flexible master clocking mode” (GCM2.VFREQ_EN = 1
B, GCM2_E) the clocking unit has to be tuned to the selected reference frequency by setting the global clock mode registers GCM(8:1) accordingly, see
formulas in GCM6_E or GCM6_T respectively. All four ports can work in E1 or T1 mode individually. After reset
the clocking unit is in “flexible master clocking mode”.
In the “clocking fixed mode” (GCM2.VFREQ_EN = 0
B) the tuning of the clocking unit is done internally so that
no setting of the global clock mode registers GCM(8:1) is necessary. All four ports must work together either
in E1 or in T1 mode.
For the calculation for the appropriate register settings see Chapter 13.3. Calculation can be performed by using
the flexible Master Clock Calculator which is part of the software support of the QuadFALC
TM.
All required clocks for E1 or T1/J1 operation are generated by the device internally. The global setting depends
only on the selected master clock frequency and is the same for E1 and T1/J1 because both clock rates are
provided simultaneously.
To meet the E1 requirements the MCLK reference clock must have an accuracy of better than ± 32 ppm. The
synthesized clock can be controlled on pins RCLK, SCLKR and XCLK.
Table 12
TAP Controller Instruction Codes
TAP Instruction
Instruction Code
BYPASS
11111111
EXTEST
00000000
IDCODE
00000100
SAMPLE
00000001
Reserved for device test
01010011