
QuadFALCTM
PEF 22554 E
E1 Registers
Data Sheet
398
Rev. 1.2, 2006-01-26
Interrupt Status Register 0
All bits are reset when ISR0 is read. If bit GCR.VIS is set, interrupt statuses in ISR0 are flagged although they are
masked by register IMR0. However, these masked interrupt stati neither generate a signal on INT (or INT1, INT2),
ISR0_E
Offset
Reset Value
Interrupt Status Register 0
xx68H
00H
Field
Bits
Type
Description
RME
7
rsc
Receive Message End - HDLC Channel 1
One complete message of length less than 32 bytes, or the last part of a
frame at least 32 bytes long is stored in the receive FIFO, including the
status byte.
The complete message length can be determined reading the RBCH,
RBCL registers, the number of bytes currently stored in RFIFO is given
by RBC(4:0). Additional information is available in the RSIS register.
RFS
6
rsc
Receive Frame Start - HDLC Channel 1
This is an early receiver interrupt activated after the start of a valid frame
has been detected, i.e. after an address match (in operation modes
providing address recognition), or after the opening flag (transparent
mode 0) is detected, delayed by two bytes. After an RFS interrupt, the
contents of
RAL1
RSIS bits 3 to 1
Are valid and can be read by the external micro controller.
T8MS
5
rsc
Receive Time Out 8 ms
Only active if multiframing is enabled. The framer has found the double
framing (basic framing) FRS0.LFA = 0B and is searching for the
multiframing. This interrupt is set to indicate that no multiframing was
found within a time window of 8 ms. In multiframe synchronous state this
interrupt is not generated. Refer also to floating multiframe alignment
window.
RMB
4
rsc
Receive Multiframe Begin
This bit is set with the beginning of a received CRC multiframe related to
the internal receive line timing. In CRC multiframe format FMR2.RFS1 =
1B or in doubleframe format FMR2.RFS(1:0) = 01B this interrupt occurs
every 2 ms. If FMR2.RFS(1:0) = 00B this interrupt is generated every
doubleframe (512 bits).