
QuadFALCTM
PEF 22554 E
E1 Registers
Data Sheet
402
Rev. 1.2, 2006-01-26
Interrupt Status Register 2
All bits are reset when ISR2 is read. If bit GCR.VIS is set, interrupt statuses in ISR2 are flagged although they are
masked by register IMR2. However, these masked interrupt statuses neither generate a signal on INT (or INT1,
ISR2_E
Offset
Reset Value
Interrupt Status Register 2
xx6AH
00H
Field
Bits
Type
Description
FAR
7
rsc
Frame Alignment Recovery
The framer has reached doubleframe synchronization. Set when bit
FRS0.LFA is reset. It is set also after alarm simulation is finished and the
receiver is still synchronous.
LFA
6
rsc
Loss of Frame Alignment
The framer has lost synchronization and bit FRS0.LFA is set. It is set
during alarm simulation.
MFAR
5
rsc
Multiframe Alignment Recovery
Set when the framer has found two CRC-multiframes at an interval of n x
2 ms (n = 1, 2, 3, and so forth) without a framing error. At the same time
bit FRS0.LMFA is reset.It is set also after alarm simulation is finished and
the receiver is still synchronous. Only active if CRC-multiframe format is
selected.
T400MS
4
rsc
Receive Time Out 400 ms
Only active if multiframing is enabled. The framer has found the
doubleframes (basic framing) FRS0.LFA = 0B and is searching for the
multiframing. This interrupt is set to indicate that no multiframing was
found within a time window of 400 ms after basic framing has been
achieved. In multiframe synchronous state this interrupt is not generated.
AIS
3
rsc
Alarm Indication Signal
This bit is set when an alarm indication signal is detected and bit
FRS0.AIS is set. It is set during alarm simulation.If GCR.SCI is set high
this interrupt status bit is set with every change of state of FRS0.AIS.
LOS
2
rsc
Loss-of-Signal
This bit is set when a loss-of-signal alarm is detected in the received bit
stream and FRS0.LOS is set. It is set during alarm simulation.If GCR.SCI
is set high this interrupt status bit is set with every change of state of
FRS0.LOS.
RAR
1
rsc
Remote Alarm Recovery
Set if a remote alarm in TS0 is cleared and bit FRS0.RRA is reset. It is
set also after alarm simulation is finished and no remote alarm is
detected.