参数资料
| 型号： | PI7C7300DNAE |
| 厂商： | Pericom |
| 文件页数： | 50/107页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE 3PORT 272-BGA |
| 标准包装： | 40 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 272-BBGA |
| 供应商设备封装： | 272-PBGA（27x27） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页当前第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 47 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
5.3.2
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS
REGISTERS
Locations accessed in the prefetchable memory address range must have true memory-
like behavior and must not exhibit side effects when read. This means that extra reads to
a prefetchable memory location must have no side effects. PI7C7300D pre-fetches for all
types of memory read commands in this address space.
The prefetchable memory base address and prefetchable memory limit address registers
define an address range that PI7C7300D uses to determine when to for- ward memory
commands. PI7C7300D forwards a memory transaction from the primary to the
secondary interface if the transaction address falls within the prefetchable memory
address range. PI7C7300D ignores memory transactions initiated on the secondary
interface that fall into this address range. PI7C7300D does not respond to any
transactions that fall outside this address range on the primary interface and forwards
those transactions upstream from the secondary interface (provided that they do not fall
into the memory-mapped I/O range or are not forwarded by the VGA mechanism).
The prefetchable memory range supports 64-bit addressing and provides additional
registers to define the upper 32 bits of the memory address range, the prefetchable
memory base address upper 32 bits register, and the prefetchable memory limit address
upper 32 bits register. For address comparison, a single address cycle (32-bit address)
prefetchable memory transaction is treated like a 64-bit address transaction where the
upper 32 bits of the address are equal to 0. This upper 32-bit value of 0 is compared to
the prefetchable memory base address upper 32 bits register and the prefetchable
memory limit address upper 32 bits register. The prefetchable memory base address
upper 32 bits register must be 0 to pass any single address cycle transactions
downstream.
Prefetchable memory address range has a granularity and alignment of 1MB. Maximum
memory address range is 4GB when 32-bit addressing is being used. Prefetchable
memory address range is defined by a 16-bit prefetchable memory base address register
at configuration offset 24h and by a 16-bit prefetchable memory limit address register at
offset 26h. The top 12 bits of each of these registers correspond to bits [31:20] of the
memory address. The lowest 4 bits are hardwired to 1h. The lowest 20 bits of the
prefetchable memory base address are assumed to be 0 0000h, which results in a natural
alignment to a 1MB boundary. The lowest 20 bits of the prefetchable memory limit
address are assumed to be FFFFFh, which results in an alignment to the top of a 1MB
block.
Note: The initial state of the prefetchable memory base address register is 0000 0000h.
The initial state of the prefetchable memory limit address register is 000F FFFFh. Note
that the initial states of these registers define a prefetchable memory range at the bottom
1MB block of memory. Write these registers with their appropriate values before setting
either the memory enable bit or the master enable bit in the command register in
configuration space.
To turn off the prefetchable memory address range, write the prefetchable memory base
address register with a value greater than that of the prefetchable memory limit address
register. The entire base value must be greater than the entire limit value, meaning that
the upper 32 bits must be considered. Therefore, to disable the address range, the upper
相关PDF资料 |
PDF描述 |
|---|---|
| PI7C8140AMAE | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| PI7C8150ANDE | IC PCI-PCI BRIDGE 2PORT 256-PBGA |
| PI7C8150BNDIE | IC PCI-PCI BRIDGE ASYNC 256-PBGA |
| PI7C8152BMAIE | IC PCI-PCI BRIDGE 2PORT 160-MQFP |
| PI7C8154ANAE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C7300EVB | 功能描述:界面开发工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| PI7C8140A | 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面开发工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| PI7C8140AMA | 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge |
| PI7C8140AMAE | 功能描述:外围驱动器与原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。