参数资料
型号: PI7C7300DNAE
厂商: Pericom
文件页数: 83/107页
文件大小: 0K
描述: IC PCI-PCI BRIDGE 3PORT 272-BGA
标准包装: 40
系列: *
应用: *
接口: *
电源电压: *
封装/外壳: 272-BBGA
供应商设备封装: 272-PBGA(27x27)
包装: 管件
安装类型: 表面贴装
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 77 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
Bit
Function
Type
Description
6
Parity Error
Response
R/W
Controls response to parity errors
0: PI7C7300D may ignore any parity errors that it detects and
continue normal operation
1: PI7C7300D must take its normal action when a parity error is
detected
Reset to 0
7
Wait Cycle
Control
R/O
Controls the ability to perform address / data stepping
0: disable address/data stepping (affects primary and secondary)
1: enable address/data stepping (affects primary and secondary)
Reset to 0
8
P_SERR# enable
R/W
Controls the enable for the P_SERR# pin
0: disable the P_SERR# driver
1: enable the P_SERR# driver
Reset to 0
9
Fast Back-to-
Back Enable
R/W
Controls PI7C7300D’s ability to generate fast back-to-back
transactions to different devices on the primary interface.
0: no fast back-to-back transactions
1: enable fast back-to-back transactions
Reset to 0
15:10
Reserved
R/O
Returns 000000 when read
14.1.4
STATUS REGISTER – OFFSET 04h
Bit
Function
Type
Description
19:16
Reserved
R/O
Reset to 0
20
Capabilities List
R/O
Set to 1 to enable support for the capability list (offset 34h is the
pointer to the data structure)
Reset to 1
21
66MHz Capable
R/O
Set to 1 to enable 66MHz operation on the primary interface
Reset to 1
22
Reserved
R/O
Reset to 0
23
Fast Back-to-
Back Capable
R/O
Set to 1 to enable decoding of fast back-to-back transactions on the
primary interface to different targets
Reset to 1
24
Data Parity Error
Detected
R/WC
Set to 1 when P_PERR# is asserted and bit 6 of command register is
set
Reset to 0
26:25
DEVSEL#
timing
R/O
DEVSEL# timing (medium decoding)
00: fast DEVSEL# decoding
01: medium DEVSEL# decoding
10: slow DEVSEL# decoding
11: reserved
Reset to 01
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