参数资料
| 型号： | PI7C7300DNAE |
| 厂商： | Pericom |
| 文件页数： | 68/107页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE 3PORT 272-BGA |
| 标准包装： | 40 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 272-BBGA |
| 供应商设备封装： | 272-PBGA（27x27） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 63 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
7.4
SYSTEM ERROR (SERR#) REPORTING
PI7C7300D uses the P_SERR# signal to report conditionally a number of system error
conditions in addition to the special case parity error conditions described in Section
7.2.3.
Whenever assertion of P_SERR# is discussed in this document, it is assumed that the
following conditions apply:
For PI7C7300D to assert P_SERR# for any reason, the SERR# enable bit must be
set in the command register.
Whenever PI7C7300D asserts P_SERR#, PI7C7300D must also set the signaled
system error bit in the status register.
In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C7300D
asserts P_SERR# when it detects the secondary SERR# input, S_SERR#, asserted and
the SERR# forward enable bit is set in the bridge control register. In addition,
PI7C7300D also sets the received system error bit in the secondary status register.
PI7C7300D also conditionally asserts P_SERR# for any of the following reasons:
Target abort detected during posted write transaction
Master abort detected during posted write transaction
Posted write data discarded after 2
24 (default) attempts to deliver (224 target retries
received)
Parity error reported on target bus during posted write transaction (see previous
section)
Delayed write data discarded after 2
24 (default) attempts to deliver (224 target retries
received)
Delayed read data cannot be transferred from target after 2
24 (default) attempts (224
target retries received)
Master timeout on delayed transaction
The device-specific P_SERR# status register reports the reason for the assertion of
P_SERR#. Most of these events have additional device-specific disable bits in the
P_SERR# event disable register that make it possible to mask out P_SERR# assertion for
specific events. The master timeout condition has a SERR# enable bit for that event in
the bridge control register and therefore does not have a device-specific disable bit.
8
EXCLUSIVE ACCESS
This chapter describes the use of the LOCK# signal to implement exclusive access to a
target for transactions that cross PI7C7300D.
相关PDF资料 |
PDF描述 |
|---|---|
| PI7C8140AMAE | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| PI7C8150ANDE | IC PCI-PCI BRIDGE 2PORT 256-PBGA |
| PI7C8150BNDIE | IC PCI-PCI BRIDGE ASYNC 256-PBGA |
| PI7C8152BMAIE | IC PCI-PCI BRIDGE 2PORT 160-MQFP |
| PI7C8154ANAE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C7300EVB | 功能描述:界面开发工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| PI7C8140A | 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面开发工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| PI7C8140AMA | 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge |
| PI7C8140AMAE | 功能描述:外围驱动器与原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
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