参数资料
型号: PI7C7300DNAE
厂商: Pericom
文件页数: 92/107页
文件大小: 0K
描述: IC PCI-PCI BRIDGE 3PORT 272-BGA
标准包装: 40
系列: *
应用: *
接口: *
电源电压: *
封装/外壳: 272-BBGA
供应商设备封装: 272-PBGA(27x27)
包装: 管件
安装类型: 表面贴装
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 85 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
14.1.27
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h
Configuration 1
Bit
Function
Type
Description
0
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
1
Memory Write
Disconnect
Control
R/W
Controls when the bridge (as a target) disconnects memory write
transactions.
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address boundary
Reset to 0
3:2
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
4
Memory Read
Flow-Through
Control
R/W
Controls whether the bridge supports memory read flow-through
0: Enable
1: Disable
Reset to 0
8:5
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
10:9
Test Mode For
All Counters at P
and S1
R/O
Controls the testability of the bridge’s internal counters.
The bits are used for chip test only.
00: all bits are exercised
01: byte 1 is exercised
10: byte 2 is exercised
11: byte 3 is exercised
Reset to 0
15:11
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
Configuration 2
Bit
Function
Type
Description
0
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
1
Memory Write
Disconnect
Control at S2
R/W
Controls when the bridge (as a target) disconnects memory write
transactions.
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address boundary
Reset to 0
3:2
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
4
Memory Read
Flow-through
Control
R/W
Controls whether the bridge supports memory read flow-through
0: Enable
1: Disable
Reset to 0
8:5
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
10:9
Test Mode For
All Counters at
S2
R/O
Controls the testability of the bridge’s internal counters.
The bits are used for chip test only.
00: all bits are exercised
01: byte 1 is exercised
10: byte 2 is exercised
11: byte 3 is exercised
Reset to 0
15:11
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
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