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参数资料
型号： PIC18LF96J65-I/PT
厂商： Microchip Technology
文件页数： 76/131页
文件大小： 0K
描述： IC PIC MCU FLASH 48KX16 100TQFP
标准包装： 90
系列： PIC® 18F
核心处理器： PIC
芯体尺寸： 8-位
速度： 41.667MHz
连通性： EBI/EMI，以太网，I²C，SPI，UART/USART
外围设备： 欠压检测/复位，POR，PWM，WDT
输入/输出数： 70
程序存储器容量： 96KB（48K x 16）
程序存储器类型： 闪存
RAM 容量： 3808 x 8
电压 - 电源 (Vcc/Vdd)： 2 V ~ 3.6 V
数据转换器： A/D 16x10b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 100-TQFP
包装： 托盘
2011 Microchip Technology Inc.
DS39762F-page 49
PIC18F97J60 FAMILY
3.0
OSCILLATOR
CONFIGURATIONS
3.1
Overview
Devices in the PIC18F97J60 family incorporate an
oscillator and microcontroller clock system that differs
from standard PIC18FXXJXX devices. The addition of
the Ethernet module, with its requirement for a stable
25 MHz clock source, makes it necessary to provide a
primary oscillator that can provide this frequency as
well as a range of different microcontroller clock
speeds. An overview of the oscillator structure is shown
in Figure 3-1.
Other oscillator features used in PIC18FXXJXX
enhanced microcontrollers, such as the internal RC
oscillator and clock switching, remain the same. They
are discussed later in this chapter.
3.2
Oscillator Types
The PIC18F97J60 family of devices can be operated in
five different oscillator modes:
1.
HS
High-Speed Crystal/Resonator
2.
HSPLL
High-Speed Crystal/Resonator
with Software PLL Control
3.
EC
External Clock with FOSC/4 Output
4.
ECPLL
External Clock with Software PLL
Control
5.
INTRC
Internal 31 kHz Oscillator
3.2.1
OSCILLATOR CONTROL
The oscillator mode is selected by programming the
FOSC<2:0> Configuration bits. FOSC<1:0> bits select
the default primary oscillator modes, while FOSC2
selects when INTRC may be invoked.
The OSCCON register (Register 3-2) selects the Active
Clock mode. It is primarily used in controlling clock
switching in power-managed modes. Its use is discussed
in Section 3.7.1 “Oscillator Control Register”.
The OSCTUNE register (Register 3-1) is used to select
the system clock frequency from the primary oscillator
source by selecting combinations of prescaler/postscaler
settings and enabling the PLL. Its use is described in
Section 3.6.1 “PLL Block”
.
FIGURE 3-1:
PIC18F97J60 FAMILY CLOCK DIAGRAM
PIC18F97J60 Family
5x PLL
FOSC<2:0>
Secondary Oscillator
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
Clock Source Option
for Other Modules
OSC1
OSC2
Sleep
Primary Oscillator
T1OSC
CPU
Peripherals
IDLEN
MUX
INTRC
Source
WDT, PWRT, FSCM
Internal Oscillator
Clock
Control
OSCCON<1:0>
and Two-Speed Start-up
Ethernet Clock
Prescaler
Postscaler
PLL/Prescaler/Postscaler
PLL
OSCTUNE<7:5>(1)
PLL
EC, HS, ECPLL, HSPLL
Note 1:
See Table 3-2 for OSCTUNE register configurations and their corresponding frequencies.
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