参数资料
型号: PIC18LF96J65-I/PT
厂商: Microchip Technology
文件页数: 86/131页
文件大小: 0K
描述: IC PIC MCU FLASH 48KX16 100TQFP
标准包装: 90
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 41.667MHz
连通性: EBI/EMI,以太网,I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 70
程序存储器容量: 96KB(48K x 16)
程序存储器类型: 闪存
RAM 容量: 3808 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 3.6 V
数据转换器: A/D 16x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-TQFP
包装: 托盘
PIC18F97J60 FAMILY
DS39762F-page 58
2011 Microchip Technology Inc.
4.2.3
RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conser-
vation of all the Run modes while still executing code.
It works well for user applications which are not highly
timing-sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting SCS<1:0> to ‘11’.
When the clock source is switched to the INTRC (see
Figure 4-3), the primary oscillator is shut down and the
OSTS bit is cleared.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
clock becomes ready, a clock switch to the primary
clock occurs (see Figure 4-4). When the clock switch is
complete, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The INTRC source will
continue to run if either the WDT or Fail-Safe Clock
Monitor is enabled.
FIGURE 4-3:
TRANSITION TIMING TO RC_RUN MODE
FIGURE 4-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q4
Q3
Q2
OSC1
Peripheral
Program
Q1
INTRC
Q1
Counter
Clock
CPU
Clock
PC + 2
PC
123
n-1
n
Clock Transition
Q4
Q3
Q2
Q1
Q3
Q2
PC + 4
Q1
Q3 Q4
OSC1
Peripheral
Program
PC
INTRC
PLL Clock
Q1
PC + 4
Q2
Output
Q3
Q4
Q1
CPU Clock
PC + 2
Clock
Counter
Q2
Q3
Note 1:
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
SCS<1:0> bits Changed
TPLL(1)
12
n-1 n
Clock
OSTS bit Set
Transition
TOST(1)
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