- 您现在的位置：买卖IC网 > PDF目录269903 > QL5820-33BPTN196C (QUICKLOGIC CORP) PCI BUS CONTROLLER, PBGA196 PDF资料下载
参数资料
| 型号： | QL5820-33BPTN196C |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA196 |
| 封装： | 12 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MO-216C, TFBGA-196 |
| 文件页数： | 2/80页 |
| 文件大小： | 1125K |
| 代理商： | QL5820-33BPTN196C |
第1页当前第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页
2006 QuickLogic Corporation
QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. L
10
Figure 4: 2,304-bit RAM Module
The number of RAM modules varies from 4 to 24 blocks for a total of 9.2 K to 55.3 K bits of RAM. Using
the two “mode” pins, designers can configure each module into 128 x 18 and 256 x 9. The blocks are also
easily cascadable to increase their effective width and/or depth (see Figure 5
).
Figure 5: Cascaded RAM Modules
The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ
and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE
ports support synchronous operation. Each port has 18 data lines and 8 address lines, allowing word lengths
of up to 18 bits and address spaces of up to 256 words. Depending on the mode selected, however, some
higher order data or address lines may not be used.
The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts
as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for
asynchronous READ operation (ASYNCRD input high).
Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by
connecting corresponding address lines together and dividing the words between modules.
A similar technique can be used to create depths greater than 256 words. In this case address signals higher
than the MSB are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs
are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.
The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with
data from an external PROM (typically for ROM functions).
MODE[1:0]
WA[7:0]
WD[17:0]
WE
WCLK
ASYNCRD
RA[7:0]
RD[17:0]
RE
RCLK
WDATA
RDATA
WADDR
WDATA
RADDR
RAM
Module
(2,304 bits)
RAM
Module
(2,304 bits)
相关PDF资料 |
PDF描述 |
|---|---|
| QL5842-33BPSN484M | PCI BUS CONTROLLER, PBGA484 |
| QT83C154XXX-L | 8-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP44 |
| QC87C251SQ | 8-BIT, UVPROM, 12 MHz, MICROCONTROLLER, CDIP40 |
| QR80C51XXX:R | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| QD80C31-S:D | 8-BIT, 20 MHz, MICROCONTROLLER, CDIP40 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL5822-33BPTN280C-5695 | 制造商:QuickLogic Corporation 功能描述: |
| QL62506PB516C | 制造商:QUICK LOG 功能描述:New |
| QL6325PQ208 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| QL6325PT280 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| QL63D5SA | 制造商:未知厂家 制造商全称:未知厂家 功能描述:InGaAlP Laser Diode |
发布紧急采购，3分钟左右您将得到回复。