参数资料
型号: QL5820-33BPTN196C
厂商: QUICKLOGIC CORP
元件分类: 总线控制器
英文描述: PCI BUS CONTROLLER, PBGA196
封装: 12 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MO-216C, TFBGA-196
文件页数: 23/80页
文件大小: 1125K
代理商: QL5820-33BPTN196C
2006 QuickLogic Corporation
QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. L
3
Configuration Space and Address Decode
The configuration space is completely customizable in the programmable region of the device.
PCI address and command decoding is performed by logic in the programmable section of the device. This
allows support for any size of memory or I/O space for back end logic. It also allows the user to implement
any subset of the PCI commands supported by the QL58x0. QuickLogic provides a reference Address
Register/Counter and Command Decode block.
PCI Interface Symbol
Figure 2 shows the graphical interface symbol numbers you have to use in your schematic design in order to
attach the local interface programmable logic design to the Target PCI core. If you are designing with a top-
level Verilog or VHDL file, use a structural instantiation of this PCI32TV2 block instead of a graphical symbol.
Table 1: IP Implemented in Programmable Logic
Essential PCI IP Cores
Logic Cells
RAM
Performance
Configuration Space/Address Decoding
110
N/A
33/66 MHz
Optional IP Cores
Logic Cells
RAM
Performance
Async 32x32 FIFO
64
2
210 MHz
Async 128x32 FIFO
88
2
190 MHz
SDRAM Controller
149
N/A
160 MHz
DDR SDRAM Controller
216
N/A
100 MHz
Pulse Width Modulation
20
N/A
303 MHz
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