参数资料
型号: QL5820-33BPTN196C
厂商: QUICKLOGIC CORP
元件分类: 总线控制器
英文描述: PCI BUS CONTROLLER, PBGA196
封装: 12 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MO-216C, TFBGA-196
文件页数: 44/80页
文件大小: 1125K
代理商: QL5820-33BPTN196C
2006 QuickLogic Corporation
QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. L
49
VDED2
I
Voltage tolerance for JTAG pins
(TDI, TMS, TCK, and TRSTB)
These pins specify the input voltage tolerance for the
JTAG input pins. The legal range for VDED2 is
between 1.71 V and 3.6 V. These do not specify output
voltage of the JTAG output, TDO. Refer to the VDED
pin section for specifying the JTAG output voltage.
VCCPLL
I
Power Supply pin for PLL
Connect to 2.5 V or 3.3. V supply. For backwards
compatibility with QL5632/QL5732 devices, connect to
2.5 V. To minimize static power consumption when
designs do not utilize the PLLs, you may connect
VCCPLL to GND. If VCCPLL is grounded, the PLL is
disabled.
PLL_RESET
I
PLL reset pin
If PLL_RESET is asserted, then CLKNET_OUT and
PLLPAD_OUT are reset to 0. This signal must be
asserted and then released in order for the
LOCK_DETECT to work.
If a PLL module is not used, then the associated
PLLRST<x> must be connected to the same voltage
as VCCPLL
Table 32: PLLOUT Pin Supply Voltage
PLLOUT
VCCIO
PLLOUT(0)
VCCIO(E)
PLLOUT(1)
VCCIO(B)
PLLOUT(2)
VCCIO(A)
PLLOUT(3)
VCCIO(F)
Table 31: Pin Descriptions (Continued)
Pin
Direction
Function
Description
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