参数资料
型号: QL5820-33BPTN196C
厂商: QUICKLOGIC CORP
元件分类: 总线控制器
英文描述: PCI BUS CONTROLLER, PBGA196
封装: 12 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MO-216C, TFBGA-196
文件页数: 32/80页
文件大小: 1125K
代理商: QL5820-33BPTN196C
2006 QuickLogic Corporation
QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. L
38
Figure 38: RAM Cell Synchronous and Asynchronous Read Timing
Table 23: RAM Cell Synchronous and Asynchronous Read Timing
Symbol
Parameter
Value
Min
Max
RAM Cell Synchronous Read Timing
t
SRA
RA setup time to RCLK: time the READ ADDRESS must be stable before the
active edge of the READ CLOCK
0.43 ns
-
tHRA
RA hold time to RCLK: time the READ ADDRESS must be stable after the active
edge of the READ CLOCK
0 ns
-
tSRE
RE setup time to WCLK: time the READ ENABLE must be stable before the
active edge of the READ CLOCK
0.21 ns
-
t
HRE
RE hold time to WCLK: time the READ ENABLE must be stable after the active
edge of the READ CLOCK
0 ns
-
tRCRD
RCLK to RD: time between the active READ CLOCK edge and the time when the
data is available at RD
-
2.25 ns
RAM Cell Asynchronous Read Timing
rPDRD
RA to RD: time between when the READ ADDRESS is input and when the DATA
is output
-
1.99 ns
tSRA
tHRA
RCLK
RA
tSRE
tHRE
tRCRD
old data
new data
RE
RD
rPDRD
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