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参数资料
| 型号： | QL5820-33BPTN196C |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA196 |
| 封装： | 12 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MO-216C, TFBGA-196 |
| 文件页数： | 56/80页 |
| 文件大小： | 1125K |
| 代理商： | QL5820-33BPTN196C |
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2006 QuickLogic Corporation
QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. L
6
Usr_RdData[31:0]
I
Data from the back-end user logic required to be presented during PCI user reads.
Cfg_CmdReg6
I
Bit 6 from the Command Register in the PCI configuration space (offset 04h). Parity
Error Response. If high, the core uses PERRN to report data parity errors. Otherwise
it never drives it.
Cfg_CmdReg8
I
Bit 8 from the Command Register in the PCI configuration space (offset 04h). SERRN
Enable. If high, the cores uses SERRN to report address parity errors if
Cfg_CmdReg6 is high.
Cfg_PERR_Det
O
Parity error detected on the PCI bus. When this signal is active, bit 15 of the Status
Register must be set in the PCI configuration space (offset 04h).
Cfg_SERR_Sig
O
System error asserted on the PCI bus. When this signal is active, the Signalled
System Error bit, bit 14 of the Status Register, must be set in the PCI configuration
space (offset 04h).
Usr_TRDY
O
Inverted copy of the TRDYN signal as driven by the PCI target interface. Valid only
within a target access.
Usr_DEVSEL
O
Inverted copy of the DEVSELN signal as driven by the PCI target interface. Valid only
within a target access.
Usr_Last_Cycle_D1
O
Active one clock cycle after the last data phase (may not with data transfer) occurs on
PCI and inactive one clock cycle afterwards.
Usr_Rdy
I
Used to delay (add wait states to) a target PCI transaction when the backend needs
additional time to provide data (read) or accept data (write). Subject to PCI latency
restrictions.
Usr_Stop
I
Used to prematurely stop a PCI target access on the next PCI clock.
Usr_STOPN
O
Copy of the STOPN signal as driven by the PCI target interface
Usr_RdPipe_Stat[1:0]
O
Indicates the number of dwords currently in the read pipeline (“00” = 0 elements, “01”
= 1 element, “11” = 2 elements). This value is important at the end of a transaction
(i.e., when Usr_Last_Cycle_D1 is active) if non-prefetchable memory is being read.
Non-prefetchable memory is defined as registers or memory elements whose value
changes when they are read. Examples are status registers which are cleared when
they are read, or FIFO memories, since consecutive reads from the same address in
these elements may not produce the same data values.
Table 2: PCI Target Interface (Continued)
Signal
I/O
Description
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