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参数资料
| 型号： | QL5820-33BPTN196C |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA196 |
| 封装： | 12 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MO-216C, TFBGA-196 |
| 文件页数： | 8/80页 |
| 文件大小： | 1125K |
| 代理商： | QL5820-33BPTN196C |
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2006 QuickLogic Corporation
QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. L
16
Figure 8: QL58x0 Device Family I/O Cell
The bi-directional I/O pin options can be programmed for input, output, or bi-directional operation. As shown
in Figure 8, each bi-directional I/O pin is associated with an I/O cell which features an input register, an input
buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one multiplexers.
The select lines of the two-to-one multiplexers are static and must be connected to either VCC or GND.
For input functions, I/O pins can provide combinatorial, registered data, or both options simultaneously to the
logic array. For combinatorial input operation, data is routed from I/O pins through the input buffer to the
array logic. For registered input operation, I/O pins drive the D input of input cell registers, allowing data to
be captured with fast, predictable set-up times without consuming internal logic cell resources. The comparator
and multiplexer in the input path allows for native support of I/O standards with reference points offset from
traditional ground.
For output functions, I/O pins can receive combinatorial or registered data from the logic array. For
combinatorial output operation, data is routed from the logic array through a multiplexer to the I/O pin. For
registered output operation, the array logic drives the D input of the output cell register which in turn drives
the I/O pin through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be
driven to the I/O pin. The addition of an output register will also decrease the Tco. Since the output register
does not need to drive the routing the length of the output path is also reduced, and static timing analysis
becomes very predictable.
The three-state output buffer controls the flow of data from the array logic to the I/O pin and allows the I/O
pin to act as an input and/or output. The buffer's output enable can be individually controlled by the logic cell
array or any pin (through the regular routing resources), or it can be bank-controlled through one of the global
networks. The signal can also be either combinatorial or registered. This is identical to that of the flow for the
output cell. For combinatorial control operation, data is routed from the logic array through a multiplexer to
the three-state control. The IOCTRL pins can directly drive the OE and CLK signals for all I/O cells within the
same bank.
E
R
Q
D
R
Q
D
E
R
Q
D
+
-
PAD
OUTPUT ENABLE
REGISTER
OUTPUT
REGISTER
INPUT
REGISTER
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