参数资料
型号: QL5820-33BPTN196C
厂商: QUICKLOGIC CORP
元件分类: 总线控制器
英文描述: PCI BUS CONTROLLER, PBGA196
封装: 12 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MO-216C, TFBGA-196
文件页数: 31/80页
文件大小: 1125K
代理商: QL5820-33BPTN196C
2006 QuickLogic Corporation
QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. L
37
Figure 37: RAM Cell Synchronous Write Timing
Table 22: RAM Cell Synchronous Write Timing
Symbol
Parameter
Value
Min
Max
RAM Cell Synchronous Write Timing
t
SWA
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the
active edge of the WRITE CLOCK
0.47 ns
-
tHWA
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the
active edge of the WRITE CLOCK
0 ns
-
tSWD
WD setup time to WCLK: time the WRITE DATA must be stable before the
active edge of the WRITE CLOCK
0.48 ns
-
t
HWD
WD hold time to WCLK: time the WRITE DATA must be stable after the active
edge of the WRITE CLOCK
0 ns
-
tSWE
WE setup time to WCLK: time the WRITE ENABLE must be stable before the
active edge of the WRITE CLOCK
0 ns
-
tHWE
WE hold time to WCLK: time the WRITE ENABLE must be stable after the
active edge of the WRITE CLOCK
0 ns
-
t
WCRD
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and
the time when the data is available at RD
-
3.79 ns
tSWA
tSWD
tSWE
tHWA
tHWD
tHWE
tWCRD
old data
new data
WCLK
WA
WD
WE
RD
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