
III PERIPHERAL MODULES 1 (SYSTEM): INTERRUPT CONTROLLER (ITC)
S1C33E07 TECHNICAL MANUAL
EPSON
III-2-59
III
ITC
These registers are used to select a trigger source for invoking each HSDMA channel.
Table III.2.7.2 HSDMA Trigger Source
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
Ch.0 trigger source
Software trigger
#DMAREQ0 input (falling edge)
#DMAREQ0 input (rising edge)
Port 0 input
Port 4 input
(reserved)
16-bit timer 0 compare B
16-bit timer 0 compare A
16-bit timer 4 compare B
I2S left
Serial I/F Ch.0 Rx buffer full
Serial I/F Ch.0 Tx buffer empty
A/D conversion completion
Port 8 input (SPI interrupt)
Port 12 input
Ch.1 trigger source
Software trigger
#DMAREQ1 input (falling edge)
#DMAREQ1 input (rising edge)
Port 1 input
Port 5 input
(reserved)
16-bit timer 1 compare B
16-bit timer 1 compare A
16-bit timer 5 compare B
I2S right
Serial I/F Ch.1 Rx buffer full
Serial I/F Ch.1 Tx buffer empty
A/D conversion completion
Port 9 input (USB PDREQ)
Port 13 input
Ch.2 trigger source
Software trigger
#DMAREQ2 input (falling edge)
#DMAREQ2 input (rising edge)
Port 2 input
Port 6 input
(reserved)
16-bit timer 2 compare B
16-bit timer 2 compare A
(reserved)
SPI transmit DMA request
Serial I/F Ch.2 Rx buffer full
Serial I/F Ch.2 Tx buffer empty
A/D conversion completion
Port 10 input (USB interrupt)
Port 14 input
Ch.3 trigger source
Software trigger
#DMAREQ3 input (falling edge)
#DMAREQ3 input (rising edge)
Port 3 input
Port 7 input
(reserved)
16-bit timer 3 compare B
16-bit timer 3 compare A
(reserved)
SPI receive DMA request
(reserved)
A/D conversion completion
Port 11 input (DCSIO interrupt)
Port 15 input
(Default: 0000)
By selecting a cause of interrupt with the HSDMA trigger set-up bit, the HSDMA channel is invoked when the
selected cause of interrupt occurs. The interrupt control bits (cause-of-interrupt flag, interrupt enable register,
IDMA request register, interrupt priority register) do not affect this invocation.
The interrupt request to the CPU by the cause of interrupt that invokes HSDMA is output two clocks (MCLK)
after the HSDMA request, so the DMA transfer and interrupt handling are performed concurrently when the CPU
runs with the instructions in the cache. However, when the interrupt handler contains an instruction that accesses a
peripheral circuit, the execution of the instruction is pending until the DMA transfer is completed since the bus is
used by the HSDMA.
Before HSDMA can be invoked by the occurrence of a cause of interrupt, it is necessary that DMA be enabled on
the HSDMA side by setting the control register for HSDMA transfer.
For details about HSDMA, refer to Section II.1, “High-Speed DMA (HSDMA).”