
VII PERIPHERAL MODULES 5 (ANALOG): A/D CONVERTER (ADC)
S1C33E07 TECHNICAL MANUAL
EPSON
VII-1-29
VII
ADC
VII.1.8 Precautions
Before setting the conversion mode, start/end channels, etc. for the A/D converter, be sure to disable ADE (D2/
0x300544). A change in settings while the A/D converter is enabled could cause it to operate erratically.
ADE: A/D Enable Bit in the A/D Control/Status Register (D2/0x300544)
In consideration of the conversion accuracy, we recommend that the A/D conversion clock be min. 16 kHz to
max. 2 MHz.
Do not start an A/D conversion when the clock supplied from the prescaler to the A/D converter is turned off, and
do not turn off the prescaler's clock output when an A/D conversion is underway, as doing so could cause the A/D
converter to operate erratically.
After an initial reset, FADE (D1/0x300287) and FADC (D0/0x300287) become indeterminate. To prevent
generation of an unwanted interrupt or IDMA request, be sure to reset these flags in a program.
FADE: A/D Conversion Completion Interrupt Cause Flag in the Port Input 4–7, RTC, A/D Interrupt Cause
Flag Register (D1/0x300287)
FADC: A/D Out-of-Range Interrupt Cause Flag in the Port Input 4–7, RTC, A/D Interrupt Cause Flag
Register (D0/0x300287)
To prevent the regeneration of interrupts due to the same cause of interrupt following the occurrence an interrupt,
always be sure to reset the cause-of-interrupt flag before setting the PSR again or executing the reti instruction.
When the A/D converter is set to enabled state, a current flows between AVDD and VSS, and power is consumed,
even when A/D operations are not performed. Therefore, when the A/D converter is not used, it must be set to the
disabled state (default 0 setting of ADE (D2/0x300544)).
When the 16-bit timer 0 compare match B signal is used as a trigger factor, the division ratio of the prescaler in
the 16-bit timer module must not be set to MCLK/1.
When using an external trigger to start A/D conversion, the low period of the trigger signal to be applied to the
#ADTRG pin must be two or more CPU operating clock cycles. Furthermore, return the #ADTRG input level
to high within 20 cycles of the A/D input clock set. Otherwise, it will be detected as the trigger for the next A/D
conversion.
Software controllable pull-up resistors are provided for the input ports. Disable the pull-up resistors of the ports
used for analog inputs.
When in break mode during ICD-based debugging, the operating clock for the A/D converter is turned off due to
the internal chip design. Therefore, the A/D converter stops operating and registers cannot be accessed for write (but
can be accessed for read).