
V PERIPHERAL MODULES 3 (INTERFACE): DIRECTION CONTROL SERIAL INTERFACE (DCSIO)
V-3-4
EPSON
S1C33E07 TECHNICAL MANUAL
V.3.4 Setting DCSIO Module
When performing data transfers via the DCSIO bus, the following settings must be made before data transfer is
actually begun:
1. Setting input/output pins
2. Setting base line and transfer rate
3. Setting data transfer direction (MSB first/LSB first)
4. Setting interrupts and IDMA/HSDMA
The following explains the content of each setting. For details on interrupt/DMA settings, refer to Section V.3.6,
“DCSIO Interrupts and DMA.”
Note: Always make sure the DCSIO module is inactive (DCSIOEN (D0/0x301800) = 0) before these
settings are made. A change of settings during operation may cause a malfunction.
DCSIOEN: DCSIO Enable Bit in the DCSIO Control Register (D0/0x301800)
Setting input/output pins
The DCSIO0 and DCSIO1 pins are used for DCSIO. Configure the Port Function Select Registers to enable
these pin functions. For details of pin functions and how to switch over, see Section I.3.3, “Switching Over the
Multiplexed Pin Functions.”
Set Line A and Line B in output mode using DIRA[1:0] (D[3:2]/0x30181C) and DIRB[1:0] (D[1:0]/0x30181C),
respectively. As shown in Table V.3.4.1, either open-drain or push-pull is selectable for output.
DIRA[1:0]: Line A Direction Select Bits in the DCSIO Port Direction Control Register (D[3:2]/0x30181C)
DIRB[1:0]: Line B Direction Select Bits in the DCSIO Port Direction Control Register (D[1:0]/0x30181C)
Table V.3.4.1 Selecting Input/Output Mode
DIRA0/DIRB0
1
0
Input/output mode
Input only
Input/push-pull output
Input/open-drain output
DIRA1/DIRB1
1
0
(Default: 0b00 = Input/open-drain output)
Setting base line and transfer rate
First, select either Line A (DCSIO0) or Line B (DCSIO1) as the base line (normally used for a clock output)
using BASESEL (D2/0x301800). Set BASESEL (D2/0x301800) to 1 when using Line A as the base line, or set
it to 0 when using Line B as the base line.
BASESEL: Base Line Select Bit in the DCSIO Control Register (D2/0x301800)
Next, configure the transfer rate of the base line using DIVRT[7:0] (D[15:8]/0x301800).
DIVRT[7:0]: DCSIO System Clock Baud Rate Setup Bits in the DCSIO Control Register (D[15:8]/0x301800)
fDCSIO_CLK
DIVRT = ——————
2
× bps
DIVRT:
DIVRT[7:0] (D[15:8]/0x301800) set value (cannot be set to less than two)
fDCSIO_CLK: DCSIO input clock frequency (= MCLK Hz)
bps:
Transfer rate (bits/second)
For example, to configure the transfer rate to 400 kbps when the CPU runs with a 48 MHz clock, set
DIVRT[7:0] (D[15:8]/0x301800) to 60 (0x3C).
The transfer rate of the other line (non-base line) can be selected as shown in Table V.3.4.2 using ADVRATE
(D3/0x301800).
ADVRATE: Non-Base Line Transfer Rate Setup Bit in the DCSIO Control Register (D3/0x301800)
Table V.3.4.2 Transfer Rate of Non-Base Line
ADVRATE
1
0
Transfer rate
Base line
× 1/8
= Base line