参数资料
型号: S1R72V17B00A
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA60
封装: 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60
文件页数: 17/45页
文件大小: 3044K
代理商: S1R72V17B00A
3. Block Diagram
4
EPSON
S1R72V17*** Technical Manual (Rev.1.6)
3.1 Multi Transceiver Macro (MTM)
This USB 2.0 transceiver macro is shared by the USB host and USB device. Incorporating an analog
circuit and high-speed logic circuit, it supports HS mode (480 Mbps) and FS mode (12 Mbps). LS mode
(1.5 Mbps) is supported only for USB hosts.
Incorporates a transmitter, receiver, termination, etc. that together comprise a USB host/device interface.
Furthermore, it has a built-in PLL that generates a 480 MHz clock needed for HS transfer. Internal
oscillator or incoming clock through CLKIN pin can be the clock source of the PLL.
3.2 Oscillator
The input clock accepts a 12 MHz or 24 MHz crystal resonator. A 1 M
feedback resistor is built-in.
3.3 Device Serial Interface Engine (Device SIE)
This block manages transactions and generates packets.
Furthermore, it controls bus events such as suspend, resume, and reset.
3.4 Host Serial Interface Engine (Host SIE)
This block schedules transactions, manages transactions, and generates packets.
Furthermore, it controls bus events such as suspend, resume, and reset.
It also detects connect/disconnect status and controls the VBUS (in cooperation with an external USB
power switch).
3.5 FIFO and FIFO Controller
These blocks comprise a channel/endpoint buffer.
3.6 CPU I/F Controller
Controls the CPU interface timing, allowing registers to be accessed properly.
3.7 DMA Controller
Controls the DMA timing of the CPU interface, allowing access to FIFO. It incorporates one DMA
channel.
3.8 Test MUX
This is a test circuit.
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