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| 型号： | S1R72V17B00A |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA60 |
| 封装： | 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60 |
| 文件页数： | 39/45页 |
| 文件大小： | 3044K |
| 代理商： | S1R72V17B00A |
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6. Functional Description
24
EPSON
S1R72V17*** Technical Manual (Rev.1.6)
6.2.3.1
Setup Stage
When a SETUP token addressed to the local node is received, the LSI automatically executes a
setup stage. Note that this setup stage is executed unconditionally, whether or not the endpoint EP0
is joined to a FIFO area.
The firmware monitors the RcvEP0SETUP status and analyze the request by reading out the
D_EP0SETUP_0 through D_EP0SETUP_7 registers to control the control transfer.
If the received request is for a control transfer with an OUT-direction data stage involved, clear the
INxOUT bit in the D_EP0Control register to direct the endpoint EP0 for OUT to permit a transition
to the data stage.
If the received request is for a control transfer with an IN-direction data stage involved, set the
INxOUT bit in the D_EP0Control register to direct the endpoint EP0 to permit a transition to the
data stage.
If the received request is for a control transfer without a data stage involved, set the INxOUT bit in
the D_EP0Control register to direct the endpoint EP0 for IN to permit a transition to the status
stage.
6.2.3.2
Data Stage and Status Stage
Go to the next stage according to the content of a request analyzed by reading out the
D_EP0SETUP_0 through D_EP0SETUP_7 registers.
If that stage is for the OUT direction, clear the INxOUT bit in the D_EP0Control register to direct it
for OUT, and then set up the D_EP0ControlOUT register as appropriate to control the stage. By the
time when the SETUP stage has finished, the ForceNAK bit must be set. Similarly, the
D_SETUP_Control.ProtectEP0 bit must be set also.
If that stage is for the IN direction, set the INxOUT bit in the D_EP0Control register to direct it for
IN, and then set up the D_EP0ControlIN register as appropriate to control the stage. By the time
when the SETUP stage has finished, the ForceNAK bit must be set. Similarly, the
D_SETUP_Control.ProtectEP0 bit must be set also.
6.2.3.3
Automatic Address Setup Function
The LSI stipulated herein has a function to automate the processing of SetAddress() requests in
control transfers at the endpoint EP0. Note that this Automatic Address Setup Function is executed
unconditionally, whether or not the endpoint EP0 is joined to a FIFO area.
The LSI checks the content of a request by reading out the D_EP0SETUP_0 through
D_EP0SETUP_7 registers in hardware. If the request is found to be a valid SetAddress() request,
the LSI shifts to processing of the status stage for that request without notifying the firmware. When
the status stage is completed, the LSI sets the relevant address in the USB_Address register and
issues a SetAddressCmp status (D_SIE_IntStat.SetAddressCmp bit) to the firmware.
The firmware monitors the SetAddressCmp status, so that when the status is issued, it can confirm
the address by reading out the USB_Address register.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S1R72V17B00A20 | 制造商:Epson Electronics America Inc 功能描述:USB HS HOST/DEVICE CONTROLLER, |
| S1R72V18 | 制造商:EPSON 制造商全称:EPSON 功能描述:Built-in pull-down resistor for downstream ports (no external circuit required) |
| S1R72V27 | 制造商:EPSON 制造商全称:EPSON 功能描述:Built-in pull-down resistor for downstream ports (no external circuit required) |
| S1R77081F | 制造商:EPSON 制造商全称:EPSON 功能描述:RSDS Transmitter/Receiver |
| S1R8ADMTBK | 制造商:Hubbell Wiring Device-Kellems 功能描述:S1R FRPT 8 ABANDONMENT PLATE |
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