- 您现在的位置：买卖IC网 > PDF目录98069 > S1R72V17B00A UNIVERSAL SERIAL BUS CONTROLLER, PBGA60 PDF资料下载
参数资料
| 型号： | S1R72V17B00A |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA60 |
| 封装： | 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60 |
| 文件页数： | 29/45页 |
| 文件大小： | 3044K |
| 代理商： | S1R72V17B00A |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页
6. Functional Description
S1R72V17*** Technical Manual (Rev.1.6)
EPSON
15
Table 6.6 lists the basic setup items for an alarm endpoint. Although this alarm endpoint currently is
not assigned to any general-purpose endpoints, it is provided to allow implementation of an endpoint
defined in the USB-defined interface. Set up these items appropriately according to the definitions
specified under the USB standard interface. Also, enable the settings made to configure a USB-defined
interface.
This alarm endpoint does not require a FIFO area.
Table 6.6 Basic Setup Items for an Alarm Endpoint
Item
Register/Bit
Description
Alarm endpoint
enable
D_EnEP_IN_H.EnEPn{n=8-15}IN,
D_EnEP_IN_L.EnEPn{n=1-7}IN,
D_EnEP_OUT_H.EnEPn{n=8-15}OUT,
D_EnEP_OUT_L.EnEPn{n=1-7}OUT
Enables an alarm endpoint
Isochronous mode
D_EnEP_IN_ISO_H.EnEPn{n=8-15}IN_ISO,
D_EnEP_IN_ISO_L.EnEPn{n=1-7}IN_ISO,
D_EnEP_OUT_ISO_H.EnEPn{n=8-15}OUT_ISO,
D_EnEP_OUT_ISO_L.EnEPn{n=1-7}OUT_ISO
To place the endpoint in Isochronous
transfer mode, set this bit to 1. For
endpoints set for Bulk or Interrupt
transfer, set this bit to 0.
6.2.2
Transactions
The LSI provides transaction execution functions in hardware and provides the firmware with the
interfaces necessary to execute transactions. The interfaces for the firmware are implemented as control
and status registers and the interrupt signals that are asserted by a status. For details on setting interrupt
assertion by status, refer to the relevant section on registers.
The LSI issues a status to the firmware for each transaction performed. However, the firmware does
not always need to manage each individual transaction. When responding to a transaction request, the
LSI inspects the FIFO to find its data quantity or free space to determine whether a data transfer can be
performed, and then performs the transaction automatically.
For an OUT endpoint, for example, the firmware can read data out of the FIFO through the CPU
interface (register read) to create a free space in the FIFO, thereby allowing OUT transactions to be
automatically executed in succession. For an IN endpoint also, the firmware can write data to the FIFO
through the CPU interface (register write) to create valid data in the FIFO, thereby allowing IN
transactions to be automatically executed in succession.
Table 6.7 lists the control items and status relating to the transaction control for the endpoint EP0.
相关PDF资料 |
PDF描述 |
|---|---|
| S1R72V18B10 | UNIVERSAL SERIAL BUS CONTROLLER, PBGA121 |
| S1R72V27B05 | UNIVERSAL SERIAL BUS CONTROLLER, PBGA60 |
| S2024B-8 | 32-BIT, DSP-CROSSBAR SWITCH, PQFP196 |
| S2025A | 32-BIT, DSP-CROSSBAR SWITCH, PQFP196 |
| S2025C-15 | 32-BIT, DSP-CROSSBAR SWITCH, PQFP196 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S1R72V17B00A20 | 制造商:Epson Electronics America Inc 功能描述:USB HS HOST/DEVICE CONTROLLER, |
| S1R72V18 | 制造商:EPSON 制造商全称:EPSON 功能描述:Built-in pull-down resistor for downstream ports (no external circuit required) |
| S1R72V27 | 制造商:EPSON 制造商全称:EPSON 功能描述:Built-in pull-down resistor for downstream ports (no external circuit required) |
| S1R77081F | 制造商:EPSON 制造商全称:EPSON 功能描述:RSDS Transmitter/Receiver |
| S1R8ADMTBK | 制造商:Hubbell Wiring Device-Kellems 功能描述:S1R FRPT 8 ABANDONMENT PLATE |
发布紧急采购，3分钟左右您将得到回复。