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参数资料
| 型号： | S1R72V17B00A |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA60 |
| 封装： | 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60 |
| 文件页数： | 37/45页 |
| 文件大小： | 3044K |
| 代理商： | S1R72V17B00A |
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6. Functional Description
22
EPSON
S1R72V17*** Technical Manual (Rev.1.6)
If the FIFO for the corresponding endpoint has a free space less than Max. packet size, the LSI
responds with NAK for the PING transaction. It also issues an OUT_TranNAK status (D_EPx{x=0,
a-e}IntStat.OUT_TranNAK bit) to the firmware.
In no case will the FIFO be updated in PING transactions.
Fig. 6.4 shows how a PING transaction is acknowledged by an ACK in device mode. In (a), the host
issues a PING token addressed to the OUT-direction endpoint present in this node. In (b), if the
FIFO has a free space equivalent to Max. packet size, the LSI responds with ACK for the PING
transaction. It also issues a status to the firmware.
PING
ACK
b
a
Host to Device
Device to Host
Fig. 6.4 PING transaction in device mode
6.2.3
Control Transfers
Control transfers at the endpoint EP0, except for SetAddress() requests, are controlled as a combination
of individual transactions. SetAddress() requests are automatically processed using the automatic
address setup function that will be described later.
Fig. 6.5 shows how a Control transfer is performed in device mode in cases in which the data stage is
set in the OUT direction. In (a), the host starts a control transfer via a SETUP transaction. The
firmware of the device analyzes the content of the request to get prepared for responding to a data stage.
In (b), the host issues an OUT transaction to execute a data stage, and the device receives data. In (c),
the host issues an IN transaction to execute a status stage, and the device sends a packet in data length
of zero back to the host.
For control transfers without data stages, the operation is executed without performing the data stage
described in this example.
Transition to the status stage is accomplished by issuing a transaction for the direction opposite to the
data stage from the host. The firmware monitors the IN_TranNAK status (D_EP0IntStat.IN_TranNAK
bit) to seize a chance for transition from the data stage to the status stage.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S1R72V17B00A20 | 制造商:Epson Electronics America Inc 功能描述:USB HS HOST/DEVICE CONTROLLER, |
| S1R72V18 | 制造商:EPSON 制造商全称:EPSON 功能描述:Built-in pull-down resistor for downstream ports (no external circuit required) |
| S1R72V27 | 制造商:EPSON 制造商全称:EPSON 功能描述:Built-in pull-down resistor for downstream ports (no external circuit required) |
| S1R77081F | 制造商:EPSON 制造商全称:EPSON 功能描述:RSDS Transmitter/Receiver |
| S1R8ADMTBK | 制造商:Hubbell Wiring Device-Kellems 功能描述:S1R FRPT 8 ABANDONMENT PLATE |
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