参数资料
型号: S1R72V17B00A
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA60
封装: 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60
文件页数: 20/45页
文件大小: 3044K
代理商: S1R72V17B00A
5. Pin Description
S1R72V17*** Technical Manual (Rev.1.6)
EPSON
7
5. Pin Description
OSC
QFP14
PFBGA8
PFBGA5
Name
I/O
RESET Pin Type
Pin Description
58
B9
B8
XI
IN
-
Analog
Input for the internal oscillator circuit
12 MHz/24 MHz
57
C9
C8
XO
OUT
-
Analog
Output for the internal oscillator circuit
To use the internal oscillator of the LSI, connect a crystal resonator and oscillator circuit to the XI and XO pins and attach
the CLKIN pin to the GND potential. To use an external clock by feeding it from the CLKIN pin, attach the XI pin to the
GND potential and leave the XO pin open.
TEST
QFP14
PFBGA8
PFBGA5
Name
I/O
RESET Pin Type
Pin Description
18
G3
H1
TESTEN
IN
(PD)
PD
Test pin (fixed low)
40
H8
ATPGEN
IN
(PD)
PD
Test pin (fixed low)
60
C7
A8
BURNIN
IN
(PD)
PD
Test pin (fixed low)
PD: Pull Down
PU: Pull Up
USB
QFP14
PFBGA8
PFBGA5
Name
I/O
RESET Pin Type
Pin Description
67
A7
A6
R1
IN
-
Analog
Internal operation setup pin
6.2 k±1% resistor connected between
this pin and VSS
73
A4
A3
DP
BI
Hi-Z
Analog
USB data line, Data+
71
A5
A4
DM
BI
Hi-Z
Analog
USB data line, Data–
3
C1
B1
VBUSFLG
IN
(PU)
Schmitt
PU
USB power switch fault detection signal
1: Normal; 0: Erratic
4
D2
C1
VBUSEN
OUT
Lo
2mA
USB power switch control signal
75
B3
C3
VBUS
IN
(PD)
PD
USB device bus detection signal
PD: Pull Down
PU: Pull Up
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