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| 型号： | S1R72V17B00A |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA60 |
| 封装： | 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60 |
| 文件页数： | 40/45页 |
| 文件大小： | 3044K |
| 代理商： | S1R72V17B00A |
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6. Functional Description
S1R72V17*** Technical Manual (Rev.1.6)
EPSON
25
6.2.3.4
Descriptor Reply Function
The LSI stipulated herein has a descriptor reply function which is effective for requests in control
transfers at the endpoint EP0 such as GetDescriptor() that requests data that has been issued a
number of times.
For requests where the data stage is for IN transfers, the firmware can make use of this function.
Before starting a response to the data stage by clearing the D_EP0ControlIN.ForceNAK bit, set the
start address of the internal data of the FIFO’s descriptor area to be returned in the D_DescAdrs_H
and _L registers or the total number of bytes of the data to be returned in the D_DescSize_H and _L
registers, and then set the D_EP0Control.ReplyDescriptor bit.
The descriptor reply function executes an IN transaction by sending back data packets in response
to the IN transaction of the data stage until the set bytes of data have all been transmitted. If an IN
transaction is issued after the set bytes of data have all been transmitted, the function responds to it
with NAK. If odd data less than Max. packet size exits, the descriptor reply function sets the
D_EP0ControlIN.EnShortPkt bit to allow for the IN transaction to be responded until all bytes of
data are sent back.
When transition to the status stage is detected by receiving an OUT token, the function clears the
D_EP0Control.ReplyDescriptor bit and issues a DescriptorCmp status
(D_EP0IntStat.DescriptorCmp bit) to the firmware. When a DescriptorCmp status is detected, the
firmware should execute the status stage.
For details about the descriptor area, refer to the relevant section in Chapter 6 on FIFOs.
6.2.4
Bulk Transfer and Interrupt Transfer
Bulk and interrupt transfers at the general-purpose endpoints EPa, EPb, Epc, Epd and EPe can be
controlled as a data flow (see 6.2.5) or as successive individual transactions (see 6.2.2).
6.2.5
Data Flow
The following describes general data flow control of OUT and IN transfers.
6.2.5.1
OUT Transfer
The data received by an OUT transfer is written to the FIFO area joined to each corresponding
endpoint. There are two methods for reading out data from the FIFO: a register read through the
CPU interface or a DMA read through the CPU interface.
To read data from the FIFO by means of a register read through the CPU interface, select a single
endpoint using the AREAn{n=0-5}Join_0.JoinCPU_Rd bit in the same area as the FIFO area joined
to each corresponding endpoint. The FIFO for the selected endpoint can be read out in the order the
data was received by using the FIFO_Rd or FIFO_ByteRd register. The bytes of data that can be
read out of the FIFO can be determined from the FIFO_RdRemain_H and FIFO_RdRemain_L
registers. Since empty FIFOs cannot be read out, be sure to check the FIFO_RdRemain_H and
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相关代理商/技术参数 |
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|---|---|
| S1R72V17B00A20 | 制造商:Epson Electronics America Inc 功能描述:USB HS HOST/DEVICE CONTROLLER, |
| S1R72V18 | 制造商:EPSON 制造商全称:EPSON 功能描述:Built-in pull-down resistor for downstream ports (no external circuit required) |
| S1R72V27 | 制造商:EPSON 制造商全称:EPSON 功能描述:Built-in pull-down resistor for downstream ports (no external circuit required) |
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