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| 型号： | S1R72V17B00A |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA60 |
| 封装： | 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60 |
| 文件页数： | 33/45页 |
| 文件大小： | 3044K |
| 代理商： | S1R72V17B00A |
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6. Functional Description
S1R72V17*** Technical Manual (Rev.1.6)
EPSON
19
Fig. 6.2 shows how a Bulk or Interrupt OUT transaction is performed in device mode in cases in
which the transaction is completed. In (a), the host issues an OUT token addressed to the
OUT-direction endpoint present in this node. In (b), the host continues to send a data packet within
Max. packet size. The LSI writes this data to the FIFO for the corresponding endpoint. In (c), the
LSI automatically returns an ACK response when it successfully received the data. It also sets up
the registers to be automatically set and issues a status to the firmware.
OUT
DATA
ACK
c
ab
Host to Device
Device to Host
Fig. 6.2 OUT transaction in device mode
6.2.2.3
Isochronous OUT Transaction
In an Isochronous OUT transaction, the LSI starts receiving data when the FIFO has free space
equal to or greater than the max packet size. Good throughput may be obtained by allocating a FIFO
area approximately twice the max packet size in order to permit the LSI to receive data while
creating a free area in the FIFO by reading out data from the FIFO by means of a register read or
DMA read through the CPU interface.
When all bytes of data have been received normally in an Isochronous OUT transaction, the LSI
issues an OUT_TranACK status for the relevant endpoint (EPx{x=a-e}IntStat.OUT_TranACK bit)
to the firmware. It also updates the FIFO and reserves an area on the assumption that the data has
been received.
When all data bytes of a short packet less than the max packet size have been received in an
Isochronous OUT transaction, the LSI issues an OUT_ShortACK status indication
(EPx{x=a-e}IntStat.OUT_ShortACK bit), in addition to the transaction-complete processing
described above. Furthermore, if the EPx{x=a-e}Control.DisAF_NAK_Short bit is cleared, the LSI
sets the EPx{x=a-e}ForceNAK bit for the endpoint.
If an error occurs in an Isochronous OUT transaction, the LSI neither receives data nor updates the
FIFO. Instead, it issues an OUT_TranErr status indication (EPx{x=a-e}IntStat.OUT_TranErr bit).
If all bytes of data for one packet could not be received in an Isochronous OUT transaction, the LSI issues
an OUT_TranNAK status indication (EPx{x=a-e}IntStat.OUT_TranNAK bit). The FIFO is not updated.
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相关代理商/技术参数 |
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| S1R72V17B00A20 | 制造商:Epson Electronics America Inc 功能描述:USB HS HOST/DEVICE CONTROLLER, |
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